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marvell. moving forward faster doc. no. mv-s105156-00, rev. 2.0 version - april 6, 2009 released cover marvell ? pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification pxa30x processor (88ap300, 88ap301, 88ap302, 88ap303) pxa31x processor (88ap310, 88ap311, 88ap312) pxa32x processor (88ap320, 88ap322) www.datasheet.co.kr datasheet pdf - http://www..net/
document conventions note: provides related information or information of special importance. caution: indicates potential damage to hardware or software, or loss of data. warning: indicates a risk of personal injury. document status draft for internal use. this document has not passed a complete technical review cycle and ecn signoff process. preliminary tapeout (advance) this document contains design specifications for a product in its initial stage of design and development. a revision of this document or supplementary information may be published at a later date. marvell may make changes to these specifications at any time without notice. contact marvell field application engineers for more information. preliminary information this document contains preliminary specifications. a revision of this document or supplementary information may be published at a later date. marvell may make changes to these specifications at any time without notice. . contact marvell field application engineers for more information. complete information this document contains specifications for a product in its final qualification stages. marvell may make changes to these specifications at any time without notice. contact marvell field application engineers for more information. doc status: technical publication: 3.10 x . y z milestone indicator: draft = 0.xx advance = 1.xx preliminary = 2.xx complete = 3.xx various revisions indicator work in progress indicator zero means document is released. for more information, visit our website at: www.marvell.com disclaimer no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retain s the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or reci pient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 2009. marvell international ltd. all rights reserved. marvell, the marvell logo, moving forward faster, alaska, fas twriter, datacom systems on silicon, libertas, link street, netgx, phyadvantage, prestera, raising the technology bar, the technology within, virtual cable tester, and yukon are registered trademarks of marvell. ants, anyvoltage, discovery, dsp switcher, feroceon, galnet, galtis, horizon, marvell makes it all possible, radlan, unimac, an d vct are trademarks of marvell. all other trademarks are the property of their respective owners. pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 4/6/09 marvell page 2 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 4/6/09 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 3 contents 1 introduction.................................................................................................................. ................11 1.1 product summary ............................................................................................................. ..............................11 1.2 document purpose ............................................................................................................ .............................12 1.3 number representation ....................................................................................................... ...........................12 1.4 naming conventions .......................................................................................................... .............................12 1.5 applicable documents ........................................................................................................ ............................12 2 functional overview ........................................................................................................... ........15 3 package information ........................................................................................................... ........19 3.1 introduction ................................................................................................................ .....................................19 3.2 packaging materials......................................................................................................... ...............................19 3.3 pxa32x processor packaging views............................................................................................ ..................19 3.3.1 pxa32x processor 456-ball vf-bga package ................................................................................19 3.3.2 pxa320 processor detailed package dimensions ..........................................................................22 3.3.3 pxa322 processor package-on-package (pop) ..............................................................................23 3.3.4 pxa322 processor detailed 15mm2 pop dimensions ....................................................................28 3.4 pxa31x and pxa30x processor package views................................................................................... .........28 3.4.1 pxa301 processor and pxa311 processor multi-chip package (mcp)..........................................28 3.4.2 pxa301 processor and pxa311 processor detailed mcp package dimensions ...........................32 3.4.3 pxa302 and pxa312 processor package-on-package (pop).........................................................32 3.4.4 pxa302 processor and pxa312 processor detailed 15mm2 pop dimensions..............................36 3.4.5 PXA300 processor and pxa310 processor discrete package (vf-bga) .......................................36 3.5 pxa30x processor package views .............................................................................................. ..................40 3.5.1 pxa303 processor 19mm2 discrete package (vf-bga).................................................................40 3.5.2 pxa303 processor detailed vf-bga package dimensions ............................................................43 3.6 pxa3xx processor family markings ............................................................................................ ...................44 3.6.1 pxa32x processor markings ................................................................................................. ...........45 4 pin listing and signal definitions ............................................................................................ .49 4.1 ball map view ............................................................................................................... ..................................49 4.1.1 pxa32x processor ball maps................................................................................................ ...........49 4.1.2 pxa31x processor ball maps................................................................................................ ...........56 4.1.3 pxa30x processor ball maps................................................................................................ ...........60 4.1.4 pxa30x processor and pxa302 processor 15mm2 multi-chip package (mcp) and package on package (pop) bottom ball map63 4.1.5 pxa303 processor 19mm2 vf-bga ball ........................................................................................ .64 4.1.6 pxa312 and pxa302 package on package (pop) top ball maps .................................................67 4.2 pin use tables .............................................................................................................. ..................................68 4.2.1 pxa32x processor pin use .................................................................................................. ............69 4.2.2 pxa31x processor pin use .................................................................................................. ............87 4.2.3 pxa30x processor pin use .................................................................................................. ..........104 4.2.4 signal type definitions ................................................................................................... ................126 5 maximum ratings and operation conditions.........................................................................127 5.1 absolute maximum ratings .................................................................................................... ......................127 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 4/6/09 marvell page 4 april 6, 2009 released 5.2 operating conditions ........................................................................................................ ............................128 6 electrical specifications ..................................................................................................... ......135 6.1 dc voltage and current characteristics ...................................................................................... .................135 6.2 oscillator electrical specifications........................................................................................ .........................138 6.2.1 32.768 khz oscillator specifications ...................................................................................... ........138 6.2.2 13.000 mhz oscillator specifications ...................................................................................... .......139 6.2.3 clock outputs ............................................................................................................. ....................140 7 ac characteristics ............................................................................................................ ........143 7.1 external memory pin interface (empi) memory timings ......................................................................... .....143 7.1.1 ddr sdram timing diagrams and specifications........................................................................144 7.2 data-flash interface (dfi) memory timing specifications..................................................................... .......146 7.2.1 variable latency i/o (vlio) timing diagrams and specifications .................................................147 7.2.2 flash memory timing diagrams and specifications.......................................................................152 7.2.3 sram timing diagrams and specifications ................................................................................... 159 7.2.4 compact flash timing diagrams and specifications .....................................................................165 7.2.5 nand timing diagrams and specifications ................................................................................... 168 7.3 quick capture camera interface timing diagrams and specifications ........................................................173 7.3.1 master-parallel timing .................................................................................................... ................173 7.3.2 master-parallel interface timing specifications........................................................................... ...173 7.3.3 slave-parallel timing..................................................................................................... .................174 7.3.4 slave-parallel interface timing parameters ................................................................................ ...175 7.4 lcd timing diagrams and specifications...................................................................................... ...............175 7.4.1 lcd passive timing ........................................................................................................ ...............175 7.4.2 lcd active panel timing................................................................................................... .............177 7.4.3 lcd smart panel timing .................................................................................................... ............179 7.5 ssp timing diagrams and specifications...................................................................................... ...............181 7.5.1 ssp slave mode timing ..................................................................................................... ............182 7.5.2 ssp mixed mode timing - processor master to clock ..................................................................183 7.5.3 ssp mixed mode timing - processor master to frame .................................................................184 7.6 ac ?97 timing diagrams and specifications ................................................................................... ..............184 7.7 usb 2.0 timing diagrams and specifications (pxa32x and pxa30x only)..................................................185 7.8 multimedia card timing diagrams and specifications.......................................................................... ........186 7.9 secure digital (sd/sdio) timing diagrams and specifications ................................................................. ..187 7.10 jtag boundary scan timing diagrams and specifications ...................................................................... ...188 8 power and reset specifications ..............................................................................................19 1 8.1 power up timings ............................................................................................................ .............................191 8.2 powerdown timings........................................................................................................... ...........................192 8.2.1 s2/d3/c4 mode timings..................................................................................................... ............192 8.2.2 s3/d4/c4 mode timings..................................................................................................... ............194 8.3 reset timing ................................................................................................................ .................................196 8.3.1 hardware reset timing ..................................................................................................... .............196 8.3.2 watchdog reset timing ..................................................................................................... ............196 8.3.3 gpio reset timing......................................................................................................... ................196 8.4 power consumption ........................................................................................................... ...........................197 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 4/6/09 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 5 figures figure 1: pxa32x processor block diagram ........................................................................................ ...........16 figure 2: pxa31x processor block diagram ........................................................................................ ...........17 figure 3: pxa30x processor block diagram ........................................................................................ ...........18 figure 4: pxa320 processor 14x14 mm vf-bga package, top view ...........................................................20 figure 5: pxa320 processor 14x14 mm vf-bga package, bottom view ......................................................21 figure 6: pxa320 processor 14x14 mm vf-bga package, side view ..........................................................22 figure 7: 14x14mm vf-bga daisy-chain substrate diagram ........................................................................22 figure 8: pxa322 processor 15-mm2 pop package, top view .....................................................................24 figure 9: pxa322 processor 15-mm2 pop package, bottom view ................................................................25 figure 10: pxa322 processor 15-mm2 pop package, side view ....................................................................26 figure 11: pxa322 15-mm2 pop daisy-chain substrate diagram ...................................................................27 figure 12: pxa301 processor and pxa311 processor 15-mm2 mcp package, top view ..............................29 figure 13: pxa301 processor and pxa311 processor 15-mm2 mcp package, bottom view.........................30 figure 14: pxa301 processor and pxa311 processor 15-mm2 mcp package, side view .............................31 figure 15: pxa301 processor and pxa311 processor 15-mm2 mcp daisy-chain substrate diagram ..........31 figure 16: pxa302 processor and pxa312 processor 15-mm2 pop package, top view ...............................33 figure 17: pxa302 processor and pxa312 processor 15-mm2 pop package, bottom view ..........................34 figure 18: pxa302 processor and pxa312 processor 15-mm2 pop package, side view ..............................35 figure 19: pxa302 processor and pxa312 processor 15-mm2 pop daisy-chain substrate diagram............35 figure 20: PXA300 processor and pxa310 processor 13-mm2 vf-bga package, top view.........................37 figure 21: PXA300 processor and pxa310 processor 13-mm2 vf-bga package, bottom view ...................38 figure 23: PXA300 processor and pxa310 processor 13-mm2 vf-bga daisy-chain substrate diagram .....39 figure 22: PXA300 processor and pxa310 processor 13-mm2 vf-bga package, side view........................39 figure 24: pxa303 processor 19-mm2 vf-bga package, top view...............................................................41 figure 25: pxa303 processor 19-mm2 vf-bga package, bottom view..........................................................42 figure 26: pxa303 processor 19-mm2 vf-bga package, side view ..............................................................42 figure 27: pxa303 processor 19-mm2 vf-bga daisy-chain substrate diagram ...........................................43 figure 28: px3xx (88ap3xx) processor family product marking information...................................................45 figure 29: pxa32x processor vf-bga product information decoder .............................................................46 figure 30: pxa32x processor configuration line decoding ......................................................................... ....46 figure 34: pxa320 processor 14mm2 vf-bga ball map, left half..................................................................50 figure 35: pxa320 processor 14mm2 vf-bga ball map, right half ...............................................................51 figure 40: pxa310 processor 13mm2 vf-bga ball map, left side..................................................................57 figure 41: pxa310 processor 13mm2 vf-bga ball map, right side ...............................................................58 figure 42: pxa31x processor 15mm2 mcp and package-on-package (pop, bottom) ball map, left side .....59 figure 43: pxa31x processor 15mm2 mcp and package-on-package (pop, bottom) ball map, right side ........................................................................................................................... ........................60 figure 44: PXA300 processor 13mm2 vf-bga ball map, left side..................................................................61 figure 45: PXA300 processor 13mm2 vf-bga ball map, right side ...............................................................62 figure 46: pxa30x 15mm2 mcp and package-on-package (pop) bottom ball map, left side .......................63 figure 47: pxa30x processor 15mm2 mcp and package-on-package (pop, bottom) ball map, right www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 4/6/09 marvell page 6 april 6, 2009 released, side ........................................................................................................................... ........................64 figure 48: pxa303 processor 19mm2 vf-bga ball map, left side..................................................................65 figure 49: pxa303 processor 19mm2 vf-bga ball map, right side ...............................................................66 figure 50: pxa302 processor and pxa312 processor pop top ball map, left side .......................................67 figure 52: ddr sdram timing diagrams ............................................................................................ ..........144 figure 53: md<31:0> to dqs write skew ........................................................................................... ............144 figure 54: clk to address/command write skew .................................................................................... ......144 figure 55: dqs to clk write skew ................................................................................................ .................145 figure 56: md<31:0> to dqs read skew ............................................................................................ ...........145 figure 57: vlio read timing diagram............................................................................................. ...............147 figure 58: vlio read timing diagram (latched addressing mode)...............................................................148 figure 59: vlio low order addressing read timing diagram .......................................................................1 48 figure 60: vlio low order addressing read timing diagram (latched addressing mode)..........................149 figure 61: vlio write timing diagram ............................................................................................ ................149 figure 62: vlio write timing diagram (latched addressing mode)...............................................................150 figure 63: vlio low order addressing write timing diagram ....................................................................... 150 figure 64: vlio low order addressing write timing diagram (latched addressing mode) ..........................151 figure 65: flash asynchronous read timing diagram ............................................................................... ....153 figure 66: flash asynchronous read timing diagram (latched addressing mode) ......................................153 figure 67: flash asynchronous low-order read timing diagram .................................................................154 figure 68: flash asynchronous low-order read timing diagram (latched addressing mode) ....................154 figure 69: flash synchronous read timing diagram ................................................................................ .....155 figure 70: flash synchronous read timing diagram (latched addressing mode) ........................................155 figure 71: flash asynchronous write timing diagrams............................................................................. .....156 figure 72: flash asynchronous write timing diagrams (latched addressing mode).....................................156 figure 73: flash asynchronous low-order addressing write timing diagrams.............................................157 figure 74: flash asynchronous low-order addressing write cycle timing diagram.....................................157 figure 75: synchronous write timings diagrams................................................................................... .........158 figure 76: synchronous write timings diagrams (latched addressing mode) ..............................................158 figure 77: sram asynchronous read timing diagram................................................................................ ..160 figure 78: sram asynchronous read timing diagram (latched addressing mode).....................................160 figure 79: sram asynchronous low-order addressing read timing diagram.............................................161 figure 80: sram asynchronous read timing diagram (non-aa/d addressing mode) .................................161 figure 81: sram asynchronous write timing diagram ............................................................................... ...162 figure 82: sram asynchronous write timing diagram (latched addressing mode).....................................162 figure 83: sram asynchronous low-order addressing write timing diagram .............................................163 figure 84: sram asynchronous low-order addressing write timing diagram (latched addressing mode).......................................................................................................................... ....................163 figure 85: compact flash 16-bit common memory read timing diagram....................................................165 figure 86: compact flash 16-bit common memory write timing diagram. ...................................................166 figure 87: compact flash 16-bit i/o memory read timing diagram..............................................................166 figure 88: compact flash 8-bit i/o space write timing diagram................................................................... 167 figure 89: nand flash program timing diagram.................................................................................... .......168 figure 90: nand flash erase timing diagram ...................................................................................... .........169 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 4/6/09 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 7 figure 91: nand flash small block read timing diagram ........................................................................... .169 figure 92: nand flash large block read timing diagram ........................................................................... .170 figure 93: nand flash status read timing diagram................................................................................ .....170 figure 94: nand flash id read timing diagram .................................................................................... .......171 figure 95: nand flash reset timing diagram ...................................................................................... .........171 figure 96: camera master-parallel timing diagram................................................................................ ........173 figure 97: camera slave-parallel timing diagram................................................................................. .........175 figure 98: lcd passive panel synchronous timing diagram......................................................................... 176 figure 99: lcd passive panel data timing diagram ................................................................................ ......176 figure 100: lcd active panel timing diagram ..................................................................................... ............178 figure 101: lcd active panel timing diagram ..................................................................................... ............178 figure 102: lcd smart panel timing diagram ...................................................................................... ...........180 figure 103: ssp master mode timing diagram ...................................................................................... ..........181 figure 104: ssp slave mode timing definitions ................................................................................... ............182 figure 105: ssp mixed mode, processor master to clock timing definitions ..................................................183 figure 106: ssp mixed mode, processor master to frame timing definitions .................................................184 figure 107: ac ?97 codec timing diagram......................................................................................... ............185 figure 108: usb 2.0 timing diagram .............................................................................................. ..................185 figure 109: multimedia card timing diagrams..................................................................................... .............186 figure 110: sd/sdio timing diagrams ............................................................................................. ................187 figure 111: jtag boundary-scan timing diagram ................................................................................... .......189 figure 112: power up reset timing ............................................................................................... ...................191 figure 113: s2/d3/c4 timing ..................................................................................................... .......................193 figure 114: s3/d4/c4 timing ..................................................................................................... .......................194 figure 115: gpio reset timing................................................................................................... ......................197 figure 116: diagram showing steps for putting pxa30x processor and pxa31x processor into high-z ........202 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 4/6/09 marvell page 8 april 6, 2009 released tables table 1: supplemental documentation............................................................................................. ..............13 table 2: package materials ...................................................................................................... ......................19 table 3: pxa320 processor 14x14 mm vf-bga package dimensions.........................................................23 table 4: pxa322 processor 15-mm2 pop dimensions ................................................................................. 28 table 5: pxa301 processor and pxa311 processor 15-mm2 mcp package dimensions ...........................32 table 6: pxa302 processor and pxa312 processor 15-mm2 pop dimensions...........................................36 table 7: PXA300 processor and pxa310 processor 13-mm2 vf-bga package dimensions......................40 table 8: pxa303 processor 19-mm2 vf-bga package dimensions ............................................................44 table 9: pxa32x processor pin usage summary......................................................................................................... 69 table 10: pxa31x processor pin usage summary.................................................................................... ......87 table 11: pxa30x pin usage summary.............................................................................................. ...........104 table 12: signal types .......................................................................................................... .........................126 table 13: absolute maximum ratings .............................................................................................. ..............127 table 14: voltage, temperature, and frequency electrical specifications ....................................................128 table 15: ddr input, output, and i/o pins ac/dc operating conditions......................................................135 table 16: mfp input, output, and i/o pins dc operating conditions............................................................136 table 17: typical 32.768 khz crystal requirements 1 ...................................................................................138 table 18: typical external 32.768 khz oscillator requirements.................................................................. .138 table 19: typical 13.000 mhz crystal requirements............................................................................... ......139 table 20: typical external 13.000 mhz oscillator requirements................................................................... 140 table 21: clk_pout specifications............................................................................................... ...............140 table 22: clk_tout specifications ............................................................................................... ...............141 table 23: standard input, output, and i/o-pin ac operating conditions ......................................................143 table 24: ddr timing specifications ............................................................................................. ................145 table 25: vlio timing specifications............................................................................................ .................151 table 26: dfi flash timing specifications ....................................................................................... ..............158 table 27: dfi sram timing specifications........................................................................................ ............164 table 28: compact flash timing specifications................................................................................... ..........167 table 29: nand flash interface program timing specifications ...................................................................1 71 table 30: master-parallel timing specifications (pxa32x processor and pxa30x processor only).............173 table 31: master-parallel timing specifications (pxa31x processor only)...................................................174 table 32: slave-parallel timing specifications.................................................................................. .............175 table 33: lcd passive panel timing specifications ............................................................................... .......176 table 34: lcd active panel timing specifications................................................................................ .........178 table 35: lcd smart panel timing specifications ................................................................................. ........180 table 36: ssp master mode timing specifications................................................................................. .......181 table 37: ssp slave mode timing specifications.................................................................................. ........182 table 38: ssp mixed mode, processor master to clock timing specifications .............................................183 table 39: ssp mixed mode, processor master to frame timing specifications............................................184 table 40: ac ?97 codec timing specifications .................................................................................... ........185 table 41: usb 2.0 timing specifications ......................................................................................... ..............186 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 4/6/09 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 9 table 42: multimedia card timing specifications................................................................................. ..........186 table 43: sd/sdio timing specifications ......................................................................................... .............188 table 44: boundary scan timing specifications ................................................................................... .........189 table 45: power up timing specifications ........................................................................................ .............192 table 46: s2/d3/c4 timing specifications ........................................................................................ .............193 table 47: s3/d4/c4 (deep sleep) timing specifications ........................................................................... ....195 table 48: gpio reset timing specifications ...................................................................................... ...........197 table 49: pxa32x processor power-consumption specifications1 ...............................................................197 table 50: pxa31x processor power-consumption specifications1 ...............................................................198 table 51: pxa30x processor power-consumption specifications1 ...............................................................199 table 52: abbreviations used in table 53 ......................................................................................... .............203 table 53: required balls for programming the package flash memory ........................................................204 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 4/6/09 marvell page 10 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 11 1 introduction the marvell pxa3xx processor family is a system-on-chip based on xscale ? microarchitecture 1 that incorporates the latest marvell advances in mobile technology over its predecessor, the marvell pxa27x processor family. the pxa32x processor, pxa31x processor, and pxa30x processor provide high-performance multimedia, low-power capabilities, and rich peripheral integration. the pxa3xx processor family (referred throughout this document as ?the processor? for simplicity) provide enhanced features compared to the pxa27x processor family, and are the first marvell applications processors to integrate a hardware video accelerator unit. the pxa3xx processor family redefines scalability by operating up to 806 mhz, providing high performance at low power for many demanding mobile applications and markets such as multimedia-enabled cellular phones, personal digital assistants (pda), and embedded devices. the pxa3xx processor family includes intel ? wireless mmx ? 2 technology, enabling high-performance, low-power multimedia acceleration with a general-purpose instruction set. marvell ? quick capture interface technology provides a flexible and powerful camera interface for capturing digital still and video images. while performance is a key feature in the pxa3xx processor family, power consumption is also a critical component. marvell ? scalable power manager technology helps enable low-power consumption with sophisticated power management capabilities. 1.1 product summary the following table describes the basic features of the processor: 1. xscale is a trademark or registered trademark of intel corporation and its subsidiaries in the united states and other countries. high-performance processor: ? xscale ? microarchitecture with intel ? wireless mmx ? 2 media enhancement technology ? 7-8 stage pipeline ? 32 kbytes instruction cache ? 32 kbytes data cache ? 2 kbytes ?mini? data cache ? extensive data buffering up to 768 kbytes of internal sram for high speed code or data storage preserved during low-power states rich serial peripheral set: ? ac ?97 audio port ? usb v. 2.0 client controller ? usb v. 1.1 client controller ? up to 3 usb v. 1.1 host controller ? usb on-the-go controller ? three high-speed uarts with hardware flow control ? sir and consumer ir infrared communications ports hardware debug features ? ieee jtag interface with boundary scan hardware performance-monitoring features with on-chip trace buffer real-time clock operating-system timers lcd controller quick capture interface controller low power: ? dynamic voltage management support ? less than 500 mw typical internal power dissipation ? core supply voltage may be reduced to 0.95 v ? five low-power modes high-performance memory controller: ? mobile ddr sdram interface ? empi and data flash interface ? up to four static chip selects ? companion-chip interface mini-lcd controller two universal subscriber identity module (usim) interface flexible clocking: ? cpu clock from 104 to 806 mhz ? flexible memory clock ratios ? frequency change capability ? functional clock gating additional peripherals for system connectivity: ? sd/sdio/mmc controller (with spi mode support) ? four ssp controllers ?two i 2 c controllers (one targeted for pmic control) ? four pulse-width modulators (pwms) ? keypad interface with both direct and matrix keys, rotary encoder support ? most peripheral pins double as gpios www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 12 april 6, 2009 released 1.2 document purpose this document constitutes the electrical, mechanical, and thermal specifications for the pxa3xx processor family. it contains a functional overview, mechanical data, package signal locations, targeted electrical specifications, and functional bus waveforms. for detailed functional descriptions other than parametric performance, refer to the pxa3xx processor family developers manual (four volumes) . 1.3 number representation all numbers in this document are decimal (base 10) unless designated otherwise. hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. for example, 107 is represented as 0x6b in hexadecimal and 0b110_1011 in binary. 1.4 naming conventions all signal and register-bit names appear in uppercase. active low items are prefixed with a lowercase ?n?. pins within a signal name are enclosed in angle brackets: external_address<31:0> ncs<1> bits within a register bit field are enclosed in square brackets: register_bitfield[3:0] register_bit[0] single-bit items have either of two states: ? clear ? the item contains the value 0b0. ? set ? the item contains the value 0b1. 1.5 applicable documents table 1 lists supplemental information sources for the pxa30x and pxa31x processor. contact a marvell representative for the latest document revisions and ordering instructions. note this document may contain shortened references to the ?pxa32x/pxa31x/pxa30x processor? or ?the processor? in some chapters. where differences exist among or between pxa3xx processors, they are called out individually. note the pxa3xx processor family consists of the following product skus: pxa30x: 88ap300, 88ap301, 88ap302, 88ap303 pxa31x: 88ap311, 88ap312 pxa32x: 88ap320, 88ap322 these product skus are not referenced in this version of the emts. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 13 table 1: supplemental documentation document title pxa3xx processor family vol. i: system and timer configuration developers manual pxa3xx processor family vol. ii: memory controller configuration developers manual pxa3xx processor family vol. iii: graphics and input controller configuration developers manual pxa3xx processor family vol. iv: serial controller configuration developers manual intel ? wireless mmx ? 2 technology developer?s guide using the intel ? wireless mmx ? 2 coprocessor with marvell ? pxa3xx processors programmers reference manual pxa3xx processor family design guide arm * architecture version v5te specification (document number arm* ddi 0100d-10), and arm * architecture reference manual (document number arm* ddi 0100b) www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 14 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 15 2 functional overview the pxa3xx processors are integrated system-on-a-chip microprocessors for high-performance, low-power portable handheld and handset devices. they incorporate the xscale ? microarchitecture with on-the-fly voltage and frequency scaling and sophisticated power management to provide industry leading mips/mw performance across its wide range of operating frequencies. the processors comply with the arm* architecture v5te instruction set (excluding floating point instructions) and follow the arm* programmers model. the multimedia coprocessor provides enhanced intel ? wireless mmx? 2 instructions to accelerate audio and video processing. the processors are available in a discrete package configuration. they provide a high degree of backward compatibility with the marvell pxa27x processor family, but they offer significant performance and feature set enhancements. the processor memory architecture offers greater flexibility and higher performance than previous core products. this architecture supports two dedicated memory interfaces for high-speed ddr sdram, vlio devices, and nand flash devices. this flexibility enables high-performance ?store- and-download? as well as ?execute-in-place? system architectures. the processor memory architecture features a memory switch that allows multiple simultaneous memory transactions among different sources and targets. for example, the processor architecture allows memory traffic between the core and ddr sdram to move in parallel with dma-generated traffic between the lcd controller and internal sram. in an architecture with a single shared system bus, these transactions block each other. the pxa32x processor also provides a 256-kbyte, unified l2 cache to maintain high memory system performance, lower power with a full feature os, and several complex multimedia applications running simultaneously. the processor incorporates an internal boot rom and a marvell ? wireless trusted transaction technology module to provide flexible boot-loading options while maintaining platform security. they have up to six 128 kbyte banks of internal sram for a combination of display frame buffer, program code, or multimedia data. each bank can be configured to retain its contents when the processor enters a low-power mode. the processor provides os timer channels and synchronous serial ports (ssps) that accept an external network clock input so that they can be synchronized to the cellular network. an integrated lcd panel controller supports active and passive displays. it permits color depths of up to 18-bits per pixels (24-bits per pixel for smart panels). the lcd controller also supports hardware cursor and two display overlays. the processor incorporates a comprehensive set of system and peripheral functions that make it useful in a variety of low-power applications. figure 1 illustrates the system-on-a-chip pxa30x processor, figure 2 illustrates pxa31x processor and figure 3 illustrates the pxa32x processor. the diagram shows a multi-port memory switch and system bus architecture with the core attached, along with an lcd controller and usb 1.1 controllers, and internal memory. the key features of all of the sub-blocks are described in the pxa3xx processor family developers manual (four volumes). www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 16 april 6, 2009 released figure 1: pxa32x processor block diagram sensor lcd panel ddr sdram ieee 802.11 cellular baseband dma controller bridge system bus #1 system bus #2 peripheral bus #1 peripheral bus #2 compactflash vlio 16-bit 32 / 16 bits sync / async flash nand sync flash 16 bit only if ddr is 16 xcvr utmi data flash interface static memory controller data flash controller intel ? quick capture camera interface mini- lcd cntrlr lcd controller 2d graphics usb2.0 high speed client memory switch driscoll intel ? wireless mmx? 2 intel xscale ? core (32k i$, 32k d$) 256 kb l2 cache dynamic memory controller static memory controller e m p i internal sram 768 kb boot rom security usim #2 usb1.1 client otg mmc/sd #2 (4-bit sdio) consumer infrared 1-wire ssp x 4 touch screen interrupt controller *coprocessor i/f intel ? msl interface gpio real- time clock timers (4f, 8s) with watchdog mmc/sd #1 (4-bit sdio) power management usim #1 ac ?97 i 2 c power i 2 c jtag usb 1.1 host uart / sir x 3 pulse-width modulators x 4 keypad interface dma controller bridge www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 17 figure 2: pxa31x processor block diagram sensor lcd panel ddr sdram system bus #1 system bus #2 peripheral bus #1 peripheral bus #2 vlio 16-bit 16 bits sync / async flash nand xcvr ulpi (otg) usb2.0 high speed client 2d graphics intel xscale? core (32k i$, 32k d$) mini- lcd cntrl lcd controller quick capture camera interface data flash interface static memory controller nand flash controller usb 1.1 host uart / sir x 3 pulse width modulators x 4 keypad interface dma controller bridge memory switch dynamic memory controller e m p i internal sram 256 kb boot rom usim #2 mmc/sd #2 (1 and 4-bit) consumer infrared 1-wire interrupt controller coprocessor i/f ssp x 4 gpio mmc/sd #1 (1 and 4-bit) usim #1 ac ?97 i 2 c real- time clock timers (4f, 8s) with watchdog power management power i2c jtag mmc/sd #3 (1 and 4-bit) video accelerator security www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 18 april 6, 2009 released figure 3: pxa30x processor block diagram sensor lcd panel ddr sdram system bus #1 system bus #2 peripheral bus #1 peripheral bus #2 vlio 16-bit 16 bits sync / async flash nand xcvr utmi usb2.0 high speed client 2d graphics intel xscale? core (32k i$, 32k d$) mini- lcd cntrlr lcd controller quick capture camera interface data flash interface static memory controller nand flash controller usb 1.1 host uart / sir x 3 pulse width modulators x 4 keypad interface dma controller bridge memory switch dynamic memory controller e m p i internal sram 256 kb boot rom usim #2 usb1.1 client otg mmc/sd #2 (1 and 4-bit) consumer infrared 1-wire interrupt controller *coprocessor i/f ssp x 4 gpio mmc/sd #1 (1 and 4-bit) usim #1 ac ?97 i 2 c real- time clock timers (4f, 8s) with watchdog power management power i2c jtag www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 19 3 package information 3.1 introduction this chapter provides the mechanical specifications for the pxa3xx processor family. 3.2 packaging materials table 2 shows the mold compound and solder ball material list. 3.3 pxa32x processor packaging views 3.3.1 pxa32x processor 456-ball vf-bga package the pxa32x processor package is a 14x14 mm, 456-pin, 0.5-mm vf-bga, as shown in figure 5 , figure 6 shows the daisy chain version of the package. table 2: package materials component material solder balls mold compound sumitomo eme-7730l 98.5 sn/1.0 ag/0.5 cu note: pb-free parts, lead has not been added intentionally, but lead may persist as an impurity below 1000 ppm www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 20 april 6, 2009 released figure 4: pxa320 processor 14x14 mm vf-bga package, top view 1234567891011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af e d top view - ball side down complete ink mark not shown ball a1 c orner aaa -b- -a- aaa -b- www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 21 figure 5: pxa320 processor 14x14 mm vf-bga package, bottom view 2625242322212019181716151413121110987654321 e bottom view - ball side up 2 s 1 s ball a 1 corn er 0.15 0.05 456x b www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 22 april 6, 2009 released 3.3.2 pxa320 processor detailed package dimensions table 3 contains both imperial (inches) and metric (millimeters) systems for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. figure 6: pxa320 processor 14x14 mm vf-bga package, side view a ccc a1 c c bbb c -c- figure 7: 14x14mm vf-bga daisy-chain substrate diagram www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 23 3.3.3 pxa322 processor package-on-package (pop) the pxa322 processor package-on-package (pop) is in a 15-by-15 mm (15 mm 2 ), 416-pin, 0.65-mm ball pitch, as shown in figure 16 , figure 17 , and figure 18 . table 3: pxa320 processor 14x14 mm vf-bga package dimensions description symbol millimeters min nom max package height a 1.000 ball height a1 0.200 0.250 0.300 ball (lead) width b 0.250 0.300 0.350 package body width d 13.950 14.000 14.050 package body length e 13.950 14.000 14.050 pitch [e] 0.500 ball (lead) count n 456 corner to ball a1 distance along d s1 0.750 corner to ball a1 distance along e s2 0.750 package edge tolerance aaa 0.15 mold flatness bbb 0.20 seating plane coplanarity ccc 0.10 www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 24 april 6, 2009 released figure 8: pxa322 processor 15-mm 2 pop package, top view 12345678910111213141516171819202122 a b c d e f g h j k l m n p r t u v w y aa ab top view - ball side down ball a1 c orner e 1 e g f d a b 160 b 1 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 25 figure 9: pxa322 processor 15-mm 2 pop package, bottom view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 e bottom view - ball side up 2 s 1 s ball a 1 corn er b 416 www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 26 april 6, 2009 released figure 10: pxa322 processor 15-mm 2 pop package, side view y a2 a c a1 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 27 figure 11: pxa322 15-mm 2 pop daisy-chain substrate diagram k8 connects to top ball land b3 l8 connects to top ball land b1 www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 28 april 6, 2009 released 3.3.4 pxa322 processor detailed 15mm 2 pop dimensions table 4 contains both imperial (inches) and metric (millimeters) systems for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. 3.4 pxa31x and pxa30x processor package views 3.4.1 pxa301 processor and pxa311 processor multi-chip package (mcp) the pxa301 processor and pxa311 processor multi-chip package (mcp) is available in a 15-by-15 mm (15 mm 2 ), 416-pin, 0.65-mm ball pitch, as shown in figure 12 , figure 13 , figure 14 and figure 15 . table 4: pxa322 processor 15-mm 2 pop dimensions description symbol millimeters min nom max package height a 0.930 ball height a1 0.180 0.280 mold compound thickness a2 0.27 0.30 0.33 smd pad for package stack b1 0.29 0.32 0.35 ball (lead) width b 0.25 0.30 0.35 package body width d 14.950 15.000 15.050 package body length e 14.950 15.000 15.050 mold cap width f 11.430 11.450 11.470 mold cap width g 11.430 11.450 11.470 pitch [e] 0.650 top package pitch [e1] 0.650 ball (lead) count n 416 seating plane coplanarity y 0.100 corner to ball a1 distance along d s1 1.000 corner to ball a1 distance along e s2 1.000 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 29 figure 12: pxa301 processor and pxa311 processor 15-mm 2 mcp package, top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 a b c d e f g h j k l m n p r t u v w y aa ab top view - ball side down e d -b- -b- ball a1 c orner -a- aaa aaa www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 30 april 6, 2009 released figure 13: pxa301 processor and pxa311 processor 15-mm 2 mcp package, bottom view 212019181716151413121110987654321 e bottom view - ball side up 2 s 1 s ball a 1 corn er b 416 8 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 31 figure 14: pxa301 processor and pxa311 processor 15-mm 2 mcp package, side view a bbb c a1 -c- ccc c figure 15: pxa301 processor and pxa311 processor 15-mm 2 mcp daisy-chain substrate diagram www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 32 april 6, 2009 released 3.4.2 pxa301 processor and pxa311 processor detailed mcp package dimensions table 5 contains both imperial (inches) and metric (millimeters) systems for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. 3.4.3 pxa302 and pxa312 processor package-on-package (pop) the pxa302 processor and pxa312 processor package-on-package (pop) is in a 15-by-15 mm (15 mm 2 ), 416-pin, 0.65-mm ball pitch, as shown in figure 16 , figure 17 , and figure 18 . table 5: pxa301 processor and pxa311 processor 15-mm 2 mcp package dimensions description symbol millimeters min nom max pxa301 processor package height a1.400 pxa311 processor package height a1.500 pxa301 processor ball height a1 0.270 0.370 pxa311 processor ball height a1 0.220 0.320 pxa301 processor mcp ball (lead) width b 0.330 0.400 0.470 pxa311 processor ball (lead) width b 0.280 0.350 0.420 package body width d 14.900 15.000 15.100 package body length e 14.900 15.000 15.100 pitch [e] 0.650 ball (lead) count n 416 corner to ball a1 distance along d s1 0.750 corner to ball a1 distance along e s2 0.750 package edge tolerance aaa 0.15 mold flatness bbb 0.20 seating plane coplanarity ccc 0.10 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 33 figure 16: pxa302 processor and pxa312 processor 15-mm 2 pop package, top view 12345678910111213141516171819202122 a b c d e f g h j k l m n p r t u v w y aa ab top view - ball side down ball a1 c orner e 1 e g f d a b 160 b 1 www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 34 april 6, 2009 released figure 17: pxa302 processor and pxa312 processor 15-mm 2 pop package, bottom view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 e bottom view - ball side up 2 s 1 s ball a 1 corn er b 416 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 35 figure 18: pxa302 processor and pxa312 processor 15-mm 2 pop package, side view y a2 a c a1 figure 19: pxa302 processor and pxa312 processor 15-mm 2 pop daisy-chain substrate diagram k8 connects to top ball land b3 l8 connects to top ball land b1 www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 36 april 6, 2009 released 3.4.4 pxa302 processor and pxa312 processor detailed 15mm 2 pop dimensions table 6 contains both imperial (inches) and metric (millimeters) systems for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. 3.4.5 PXA300 processor and pxa310 processor discrete package (vf-bga) the PXA300 processor and pxa310 processor packages are available in a 13-by-13 mm (13 mm 2 ) vf-bga, 400-pin, 0.5-mm ball pitch configuration, as shown in figure 20 , figure 21 , and figure 22 . table 6: pxa302 processor and pxa312 processor 15-mm 2 pop dimensions description symbol millimeters min nom max package height a 0.930 ball height a1 0.180 0.280 mold compound thickness a2 0.27 0.30 0.33 smd pad for package stack b1 0.29 0.32 0.35 ball (lead) width b 0.25 0.30 0.35 package body width d 14.950 15.000 15.050 package body length e 14.950 15.000 15.050 mold cap width f 11.430 11.450 11.470 mold cap width g 11.430 11.450 11.470 pitch [e] 0.650 top package pitch [e1] 0.650 ball (lead) count n 416 seating plane coplanarity y 0.100 corner to ball a1 distance along d s1 1.000 corner to ball a1 distance along e s2 1.000 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 37 figure 20: PXA300 processor and pxa310 processor 13-mm 2 vf-bga package, top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a b c d e f g h j k l m n p r t u v w y aa ab ac ad top view - ball side down complete ink mark not shown e d ball a1 c orner -a- aaa -b- -b- aaa www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 38 april 6, 2009 released figure 21: PXA300 processor and pxa310 processor 13-mm 2 vf-bga package, bottom view 242322212019181716151413121110987654321 e 2 s 1 s ball a 1 corn er bottom view - ball side up 0.05 0.15 b 400 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 39 figure 22: PXA300 processor and pxa310 processor 13-mm 2 vf-bga package, side view figure 23: PXA300 processor and pxa310 processor 13-mm 2 vf-bga daisy-chain substrate diagram a a1 bbb c -c- ccc c c www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 40 april 6, 2009 released 3.5 pxa30x processor package views 3.5.1 pxa303 processor 19mm 2 discrete package (vf-bga) the pxa303 processor package is provided in a 19-by-19 mm (19 mm 2 ) vf-bga, 409-pin, 0.8-mm ball pitch configuration, as shown in figure 24 , figure 25 , figure 26 , and figure 27 . tab le 7 contain both imperial (inches) and metric (millimeters) for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. table 7: PXA300 processor and pxa310 processor 13-mm 2 vf-bga package dimensions description symbol millimeters min nom max package height a 1.000 ball height a1 0.18 0.250 0.300 ball (lead) width b 0.260 0.300 0.340 package body width d 12.900 13.000 13.100 package body length e 12.900 13000 13.100 pitch [e] 0.500 ball (lead) count n 400 corner to ball a1 distance along d s1 0.750 corner to ball a1 distance along e s2 0.750 package edge tolerance aaa 0.10 mold flatness bbb 0.10 seating plane coplanarity ccc 0.08 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 41 figure 24: pxa303 processor 19-mm 2 vf-bga package, top view www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 42 april 6, 2009 released figure 25: pxa303 processor 19-mm 2 vf-bga package, bottom view figure 26: pxa303 processor 19-mm 2 vf-bga package, side view www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 43 3.5.2 pxa303 processor detailed vf-bga package dimensions table 8 contains both imperial (inches) and metric (millimeters) systems for the package dimensions. the imperial data has been rounded down. the metric measurements are exact and do not contain any rounding. marvell recommends using the metric (millimeters) data. figure 27: pxa303 processor 19-mm 2 vf-bga daisy-chain substrate diagram www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 44 april 6, 2009 released 3.6 pxa3xx processor family markings each pxa30x and pxa31x processor includes markings on top of the package. figure 28 contains the processor product marking information that explains each part of the marking. there are two different decoders, one for samples, and one for production material. table 8: pxa303 processor 19-mm 2 vf-bga package dimensions description symbol millimeters min nom max package height a 1.560 ball height a1 0.350 0.450 package body thickness a2 1.060 ball (lead) width b 0.450 0.500 0.550 package body width d 18.900 19.000 19.100 package body length e 18.900 19.000 19.100 pitch [e] 0.800 ball (lead) count n 409 seating plane coplanarity y 0.140 corner to ball a1 distance along d s1 0.700 corner to ball a1 distance along e s2 0.700 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 45 3.6.1 pxa32x processor markings each PXA300 processor or pxa310 processor includes markings on top of the package. figure 29 contains a ?product information decoder? that explains what each part of the marking means. note that there are two different decoders, one for samples and one for production material. figure 30 contains the ?configuration line decoder? that explai ns the configuration line for production material. figure 28: px3xx (88ap3xx) processor family product marking information www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 46 april 6, 2009 released figure 29: pxa32x processor vf-bga product information decoder figure 30: pxa32x processor c onfiguration line decoding sample markings t h g p a m h n 1 b package type: rt = vf bga (pb - free) division (chg) stepping r c h 1 b h 1 b ap = application processor blank monahans processor family production markings p x a 3 2 b 0 1 8 c 6 0 xscale-based ? processor processor family stepping blank speed temp range c f g 1 a configuration marking boot configuration 1 = x16 nand 2 = x8 nand 4 = xip nor on the dfi power bin a = low power bin b = standard bin c f g 1 a configuration marking boot configuration 1 = x16 nand 2 = x8 nand 4 = xip nor on the dfi power bin a = low power bin b = standard bin www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 47 figure 32: pxa32x processor daisy chain samples markings figure 31: pxa32x processor engineering sample markings product lot # qdf # i rtchgapmnhb1 fpo# q123 es b1 m c ?05 korea pin 1 indicator e1 pb-free indicator product lot # qdf # i rtchgapmnhb1 fpo# q123 es b1 m c ?05 korea pin 1 indicator e1 pb-free indicator e1 pb-free indicator laser mark on top side of package laser mark on top side of package 14x14mm 456l daisy chain korea pin 1 indicator www.datasheet.co.kr datasheet pdf - http://www..net/
px3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 48 april 6, 2009 released figure 33: pxa32x processor production markings product lot # boot configuration and power bin i pxa320b1c806 fpo# cfg1a m c ?05 korea pin 1 indicator e1 pb-free indicator product lot # boot configuration and power bin i pxa320b1c806 fpo# cfg1a m c ?05 korea pin 1 indicator e1 pb-free indicator e1 pb-free indicator laser mark on top side of package www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 49 4 pin listing and si gnal definitions this chapter describes the signals and pins for the pxa3xx processor family. many of the package pins are multiplexed so that they can be configured for use as a general-purpose i/o signal or any one of the alternate functions using the gpio alternate-function select registers. some signals can be configured to appear on one of several different pins using alternate function controls. 4.1 ball map view in the following ball map figures, the lowercase letter ?n?, which normally indicates negation, appears as uppercase ?n?. ?rfu? means ?reserved for future use?. nc means ?no connect?. do not connect these pins. the balls highlighted in yellow show the difference between the pxa30x and pxa31x processor. 4.1.1 pxa32x processor ball maps 4.1.1.1 pxa320 processor 456-ball vf-bga ball map figure 34 and figure 35 show the ball map for the 456-ball vf-bga pxa320 processor discrete package. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 50 april 6, 2009 released figure 34: pxa320 processor 14mm 2 vf-bga ball map, left half 12345678910111213 a nc nc usbotg_ n usbotg_ p u sbh1_n usbh1_ p pwr_ en tms vss vcc_bba tt ng pio _r eset pw r _ sd a t e s t a b n c md1 md0 tck vss_usb tdi nbatt_f ault pw r_out vss_bba tt pxtal_in vss_osc 13m vc t c x o_ en gpi o4_2 b c md4 md2 dqm0 md 3 vcc_usb clk_tou t pwr_ cap 1 txtal_o ut nreset _ out px t al _ o ut pw r_scl t est clk gpi o2_2 c d md7 dqs0 md5 vc c_mem tdo ntr st pwr_ cap 0 txtal_ in vcc_bg vss_ bg clk_pou t gpi o5 _2 gpi o127 d e dqs1 md6 md8 vss_ mem sys_en nreset vcc _mvt vcc_o sc 13m vcc_sra m vcc_io1 vss_io1 gpio0 _2 gpio125 e f dq m1 md1 0 md9 vc c_mem ext_wak eup1 f g md14 md1 3 md11 vss_ mem ext_wak eup0 g h ma3 md1 5 md12 vc c_mem vcc_mvt h j ma 1 m a 2 vc c _ s r a m vss_ mem vcc_ mem j k ma14 sdma10 rf u_k3 ma0 vcc_ mem k l nsdcs0 ma1 3 ma12 ma15 vss_mem vss vss vc c _ a pp s l m sdcl k0 sdcke nsdw e vcc_mvt vcc_ mem vss vss vc c _ a pp s m n sdcl k1 n sdr as ma8 nsdcs1 vss_mem vcc_app s vcc_app s vss n p ma5 ma9 ma7 ma11 vcc_ mem vcc_app s vcc_app s vss p r rco mp_ d dr rf u_r2 ma6 nsdcas vss_mem vss vss vc c _ a pp s r t rfu_ t1 r fu_t 2 rf u_t 3 ma4 vcc_ mem vss vss vc c _ a pp s t u rf u_u1 rf u_u2 rf u_u3 rfu_ u4 vss_mem u v md18 dqm2 md17 md16 vss_mem v w md19 dqs2 md23 vcc_mvt vcc_ mem w y md20 md2 4 md22 vss vcc_ mem y aa md21 dqs3 dqm3 md25 vss_mem aa ab md26 md31 md30 md27 vcc_mem df_ale_ n we2 vcc_df vcc_ mvt vss d f_io8 vcc_sra m vss df_io12 ab ac md28 gpio2 gpio1 gpio0 vss_mem vss_df vss_df d f_addr 0 vcc_d f vss_df df_io1 df_io4 df_io15 ac ad md29 gpio3 gpio4 rfu_ad4 df _cle_ noe vcc_df df_ nre d f_addr 1 df_ io 0 d f_io2 df_io 11 df _io13 vss_df ad ae n c nc nxcvren n be0 df_int _r nb df _ncs0 nlua nlla df _addr 3 df_ io 10 vcc_df df _io 6 vcc_ df ae af nc nc df_ale_n we1 df _sclk_ e nbe1 df _ncs1 df _nw e d f_addr 2 df_ io 9 d f_io3 vss_ df df _io 5 df_ io 7 af 12345678910111213 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 51 4.1.1.2 pxa322 processor 15mm 2 package on package (pop) bottom ball map figure 36 and figure 37 show the bottom ball map for the bottom pxa322 processor pop package. figure 35: pxa320 processor 14mm 2 vf-bga ball map, right half 14 15 16 17 18 19 20 21 22 23 24 25 26 a gpio3_2 gpio126 gpio1 23 gpio11 4 vcc _tsi gpio109 gpio1 06 gpio10 2 gpio101 gpio100 gpio99 nc nc a b gp io 1_2 vc c_p ll g pi o1 21 gp i o11 9 gp io 113 g p io 110 g pi o1 07 gp i o10 3 v cc_ io 6 g pi o9 4 gp i o98 gp io 97 nc b c vss_pl l gpio122 gpio1 18 gpio11 5 vss_tsi gpio112 vcc_io6 gpio10 5 vss_io6 gpio9 5 gpio96 gpio88 gpio90 c d gpio 124 vcc_io1 vc c _ s r a m gpio11 6 tsi_ym tsi_xm vss_io6 gpio93 gpio87 gpio9 2 gpio91 gpio89 gpio84 d e gpio120 vss_io1 gpio1 17 tsi_yp tsi_xp gpio111 vcc _mvt gpio10 8 gpio104 gpio8 5 gpio86 gpio81 gpio82 e f gpio83 gpio8 0 vcc_msl gpio79 vss_msl f g gpio78 vcc_mvt gpio77 vss vss g h g pio1 5_2 g pi o7 5 gpi o76 g pio 17_2 vcc_ sra m h j gpio73 gpio74 gpio16_2 vss_lcd vcc_lcd j k g pio 66 g pi o7 1 gpi o72 g pio 14_2 g pio 70 k l vcc_app s vss vss g pio1 1_2 g pi o6 9 gpi o67 gpio 64 g pio 68 l m vcc_app s vss vss gpio9_2 vss_lcd gpio63 gpio13_2 gpio65 m n vss vcc_app s vcc_app s vss g pio 8_2 vcc_lcd g pio 10_2 g pio1 2_2 n p vss vcc_app s vcc_app s vcc_mvt gpio7_2 gpio61 gpio6 _2 gpio62 p r vcc_app s vss vss gpio57 gpio6 0 gpio59 vss_ci vcc_c i r t vcc_app s vss vss gpio53 gpio58 gpio56 vcc_app s vss t u gpio51 gpio5 2 vss_ ci gpio54 gpio55 u v g pio 48 g pio5 0 vc c_ci vcc_app s vss v w gpio43 vcc_io4 gpio45 gpio10 gpio49 w y gpio39 gpio4 1 vss_io4 gpio47 gpio46 y aa g pio 32 g pi o4 0 gpi o42 gpio 44 vss aa ab df_io14 gpio7 gpio11 gpio12 vcc_ io3 gpio16 gpio19 vcc_ car d1 g pio 28 vss_io4 vcc_io4 gpio 37 vcc_mvt ab ac vcc_app s gp io 8 vcc_app s gpio14 vss_pll gpio17 vcc_app s gpio 20 g pio 22 g pi o3 0 gpi o34 gpio 36 g pio 38 ac ad vss vc c_mvt vss vss vss vcc_app s vss_c ar d1 vss g pio 25 g pi o2 7 gpi o31 gpio 33 g pio 35 ad ae gp i o6 vs s vcc_app s vss_io3 vcc_pll vss gpio18 vss gpio24 vcc_car d2 vss_ car d2 gp io 29 nc ae af gp i o5 vcc_app s gpio9 gpio13 vcc_ app s gp i o15 vcc_app s vc c _ a pp s gpio21 gpio23 gpio26 nc nc af 14 15 16 17 18 19 20 21 22 23 24 25 26 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 52 april 6, 2009 released figure 36: pxa322 processor 15mm 2 pop bottom ball map, left half 12345 67891011 a n c_a1 nc_a2 vss_ df rfu_a4 tdi pw r_en txtal_ in txtal_ out vss_osc 13 m pw r_sda gpio4_2 a b n c_b1 vcc_mem rf u_b3 vc c _ d fc o re df_nc s1 vcc_u sb nreset _in pw r_cap0 vcc_df rf u_b10 rf u_b11 b c vss_mem md1 rfu_c3 vss usbotg_p clk_tout pw r_out vss_bbatt vss_bg df _cle_n oe gpi o2_2 c d vss md0 vcc_mem rf u_d4 usbo tg _n rfu_ d6 ng pio _res et df_ ale_n we1 cl k_ po ut t est vss_io1 d e md3 md2 vss_u sb tck u sbh1_ n usbh1 _p tms vcc_apps nb at t_ fa u lt pxt al_o ut gpi o5_2 e f md5 md4 vcc _mvt vcc_mvt ma2 tdo nt rst vss pxt al_in vcc_o sc1 3m vctcxo_e n f g vcc_sram vcc_sram md7 ma3 md9 md11 sys_en pwr_cap1 nreset_o ut vcc_bg gpio1_2 g h vss_mem dqm1 nsdw e md1 5 md13 ext_wake up1 rfu _h7 ex t _w ak e up0 vc c_bbatt gpio127 pwr_ scl h j md6 dqs0 ma1 ma1 4 vss ma12 n sdc s1 ma0 j k d qm0 vss_ mem sd ma10 nsdcs0 vcc_ mem ma6 ma4 g pio1 19 k l rc omp_ dd r ma11 vcc_mem n sdr as vcc_ apps vcc _apps rf u_l7 vcc _mvt l m vss_mem dqs1 vcc_mem vss vcc_ apps sd clk1 vcc_mem gpio4 m n md10 vcc_mem vss vcc_mem md17 vcc _apps vcc_apps ma13 n p vss_mem vcc_mem vcc _mvt vcc_mvt vcc_ apps df_ io1 vss_ mem df_ncs0 vc c_sram df_io15 gpio5 p r vss_mem md8 md24 vss_mem vss_mem gpio3 gpio11 1 df_io1 4 gpio109 gpio7 vss_lcd r t vss_mem md12 dqm2 md2 9 vcc_df nbe0 d f_a le_n we2 df _nw e df _io4 df_io3 df _io 12 t u vss sdcke g pio 0 md2 8 md31 df _nre df _io 2 nlua df _io0 df_io5 vss u v vss vss g pio 2 gpio 1 nxc vren vcc_ df vss df _addr2 df _io8 df_io6 df_io 9 v w df _int _rn b md14 md22 dq m3 df _sclk_e vss_df df _addr0 df _addr1 md 27 df_io7 vss w y n c_y1 sdclk0 md16 md2 6 md18 nbe1 nc_y7 df _addr3 df_ io 11 vss_df md25 y aa nc_aa1 nc_aa2 vcc_memc ore md1 9 m d30 m d20 m d21 nlla md 23 dqs2 dqs3 aa 12345 67891011 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 53 figure 37: pxa322 processor 15mm 2 pop bottom ball map, right half 1 2 13 14 15 1 6 17 18 19 20 2 1 a gpio0_2 gpio12 6 gpio1 20 gpio116 tsi_xp_hv gpio108 gpio10 4 vcc_ sram nc_a20 nc_a21 a b gp i o122 gp i o11 8 g pi o1 14 v cc_i o1 gp io 110 t s i_y p _hv gp i o10 2 g pi o1 06 v s s _df nc_b 21 b c vss _pll gpio12 4 t si_ym _hv g pio 112 gpio 105 gpi o100 gp io 99 g pi o1 03 df _nw p g pi o9 5 c d gpio121 lock_pre vss_tsi gpio107 gpio8 8 gpio90 gpio10 1 gpio97 gpio87 gpio9 6 d e vcc _tsi gpio12 5 vss vcc_io6 gpio9 4 vcc_mvt gpio91 vss_io6 gpio93 gpio9 2 e f vcc_pll gpio3_ 2 vcc_ sram tsi_ xm_hv gpio8 4 gpio86 gpio85 gpio89 gpio75 gpio7 9 f g testcl k gpio12 3 gpio1 17 gpio76 gpio7 8 vss_msl gpio83 vc c_msl gpio81 gpio7 7 g h gp i o113 gp i o11 5 gp i o80 gp i o16_ 2 gp i o14 _2 g p io 74 gp io 73 gp io 17_2 gp i o71 gp i o15 _2 h j gpio70 gpi o68 g pio7 2 g pio 66 gp io 65 gpi o67 gp io69 vs s_lcd j k gpio98 g pio 9_2 g pio8 2 g pio 64 vcc _lcd gpio63 vcc_lc d g pio6 1 k l g pi o7 _2 gpi o60 g pio6 2 g pio1 3_2 g pio 11_2 gp io 10_2 g pio 8_2 gp io12 _2 l m gp i o52 v cc_ci g pi o5 6 g p io 54 gp io 53 gp i o57 gp i o59 ma 5 m n vcc_apps vcc_mvt vss_ci gpio58 ma15 gpio55 gpio6_2 ma7 n p gp i o9 gp io 14 gp i o10 gp i o50 g pi o4 5 v s s gp io 47 gp i o49 gp i o48 v ss p r vcc_pll df_io10 vss_card 1 gp i o43 g pi o4 1 v ss _i o4 gp io 46 gp i o44 gp i o42 g pi o5 1 r t v ss _i o3 gp io 16 d f_i o1 3 gp i o39 g pi o3 7 g p io 36 gp io 34 gp i o40 gp i o38 ns dca s t u g p io 31 gp io 12 gp i o17 gp i o20 g pi o2 9 g p io 35 v cc_i o4 gp i o28 gp i o30 ma 9 u v vcc_ apps gpio11 vss vcc_apps gpio2 7 gpio22 gpio33 vss_card 2 gp i o32 ma 8 v w gp i o6 vc c _ a pp s v ss _ p l l gp i o1 8 g pi o1 9 vcc_card 2 gpio25 gpio24 nd_rst vss_mem w y vss_df gpio13 gpio15 vcc_apps vcc_ apps gpio23 vss rfu_ y1 9 rfu _y20 nc_y21 y aa gpio8 vc c_io3 vcc_apps vcc_apps gpio2 1 vcc_card 1 vss gpio26 nc_aa20 nc_aa21 aa 1 2 13 14 15 1 6 17 18 19 20 2 1 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 54 april 6, 2009 released 4.1.1.3 pxa322 15mm 2 package-on-package (pop) top ball map figure 38 and figure 39 show the top ball map for the 416-ball bottom pxa322 processor pop package. notes: 1. the lock_pre ball (d13) connects directly to the a14 on the top package. consult the datasheet for the top package memory device for appropriate requirements for this pin. 2. the df_nwp ball (c20) connects directly to c21 and f22 on the top package. consult the datasheet for the top package memory device for appropriate requirements for these pins. 3. the nd_rst ball (w20) connects directly to y21 on the top package. consult the datasheet for the top package memory device for appropriate requirements for these pins 4. the vcc_df balls (v6, t5 and b9) connect to the vcc_dfq balls (b9, b15, b21 and ab21) on the top package and are powered from the vcc_df power domain. these balls are used for the io voltage domain for the device connected to the data flash interface (dfi). 5. the vcc_dfcore ball (b4) is directly connected to the vcc_df balls (b4, b20, aa3 and aa12) on the top package. a seperate power supply can be used for this ball in order to keep the core voltage on while the processor is in s3/d4/c4 power mode. if this is not needed for the device connected to the dfi bus connect this pin to the vcc_df power domain. 6. the vcc_mem balls (b2, d3, k5, l3, n2, n4, m3, m7 and p2) are connected to the vcc_memq balls (e2, h2, m2, u2, aa5, aa8, aa15 and aa18) on the top package and are powered from the vcc_mem power domain. these balls are used for the io voltage domain for the ddr sdram. 7. the vcc_memcore ball (aa3) is connected to the vcc_mem balls (b2, j21, p2, aa21 and ab2) on the top package. a separate power supply can be used for this ball in order to keep the ddr sdram core voltage on while the processor is in s3/d4/c4 power mode. if power does not need to be supplied to the core voltage for the ddr sdram while the processor is in s3/d4/c4 connect this pin to the vcc_mem power domain. figure 37: pxa322 processor 15mm 2 pop bottom ball map, right half www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 55 figure 38: pxa322 processor 15mm 2 pop top ball map, left side 1 2 3 4 5 6 7 8 9 10 11 a nc vss_ mem df_io1 vss_df df_io3 df_ io5 df_io7 df_io9 vss_df df _cle_n oe df _io11 a b vss_mem vcc_mem df _io0 vcc_df df_io2 df_ io 4 df _io 6 df _io8 vcc_df q df _ale_n we1 df _io10 b c df_nw e df _int_r n b c d md 1 m d 0 d e vss_mem vcc_ memq e f md 3 m d 2 f g md 5 m d 4 g h vss_mem vcc_ memq h j md 7 m d 6 j k dqm0 dq s0 k l dqm1 dq s1 l m vss_mem vcc_ memq m n md 9 m d 8 n p vss_mem vcc_mem p r md11 md10 r t md13 md12 t u vss_mem vcc_ memq u v md15 md14 v w sdcke sdclk0 w y nc sdclk1 y aa nc vss_df vcc_df md1 6 vcc_memq md18 md20 vcc_memq md 22 dqs2 df_sclk_s a a ab nc vcc_mem vss_ df md1 7 vss_mem md19 md21 vss_mem md 23 d qm2 nc ab 1 2 3 4 5 6 7 8 9 10 11 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 56 april 6, 2009 released 4.1.2 pxa31x processor ball maps 4.1.2.1 pxa310 processor 13mm 2 vf-bga ball map figure 40 and figure 41 show the bottom ball map for the pxa310 processor 13mm 2 discrete package. the balls highlighted in yellow have different functionality on the pxa30x processor. figure 39: pxa322 processor 15mm 2 pop top ball map, right side 12 13 14 15 16 17 18 19 20 21 22 a df_io13 df_io15 lo c k _p r e vss_df nc nc nc nc nc vss_df nc a b df_io12 df_io14 nc vcc_dfq nc nc nc nc vcc_df vcc_dfq vss_df b c df_ n wp n c c d gpio3 gpio4 d e df_ncs0 df_ncs1 e f df_nre df_nwp f g df_ale_ nwe1 nc g h nsdwe df_cle_ no e h j vcc_mem vss_mem j k ma 0 ma 1 k l ma 2 ma 3 l m ma 4 ma 5 m n ma 6 ma 7 n p ma14 ma15 p r nsdcs0 nsdcs1 r t nsdras nsdcas t u ma 8 ma 9 u v sdma10 ma11 v w ma12 ma13 w y nd_rst vss_mem y aa vcc_df dqs3 md24 vcc_memq md 2 6 md 2 8 vc c _ me m q md30 nlla vcc_mem nc a a ab vs s_df dqm 3 m d25 vss_mem md 2 7 md 2 9 vss_ mem md31 nc vcc_dfq nc ab 12 13 14 15 16 17 18 19 20 21 22 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 57 figure 40: pxa310 processor 13mm 2 vf-bga ball map, left side 123456789101112 a nc nc rfu _a3 vcc_bias t ck clk_t out pw r_ cap 0 nreset _o ut pxt al _in pw r_scl vcc_i o1 g pio 1_2 a b nc rfu _b2 rfu _b3 rf u_b4 t di n reset pw r_o ut vc c _ os c 1 3m pxtal_o u t vctcxo_e n vss_io 1 cl k_ po ut b c vss_mem vss_mem rfu_ c3 tdo pwr_en nbatt_fa ult tx ta l_ in txtal_ou t vcc_ bg vss_ osc1 3m vcc _pll gpio127 c d md 0 vcc _me m tm s d e md 1 md 2 vc c _me m n t r s t ext_ wake up0 vss vcc_bbat t ng pio _re se t testclk vcc_apps vss e f md3 d qm0 vcc _mem vss_ mem sys_en pw r_ cap 1 vss_bbat t vcc _mvt vss_bg pwr _sda g pio 125 f g md4 md5 dq s0 vc c_mem vss_ mem g h md7 ma2 md 6 vss_ mem vcc_ mvt vss vss vcc_apps vss test h j ma6 ma15 ma14 vc c_mem vss_ mem vss j k sdma10 ma8 ma4 vc c_mem vss_ mem vcc_apps k l sdc lk0 sd clk1 ma12 vc c_apps vss_ mem vss l m ma0 nsdcs1 nsdcs0 ma13 vss vss m n ma9 ma11 ma7 vc c_mem vss_ mem vss n p rc omp_d dr nsdras ma5 ma3 vcc_ mvt vss p r r fu_r 1 sdcke nsdw e ma1 vss_ mem vcc_apps r t md9 md8 nsdcas vc c_mem vss_ mem vss t u d qm1 md11 md10 vss vcc_ mvt vss vss vcc_apps vss vss u v md13 md12 dqs1 vc c_mem vss_mem v w gp i o0 m d14 m d15 nc df _cle_n oe nc nc nc df _ncs0 vcc_sra m nc w y gpio2 vcc _mem vss_mem vss_df vcc _df df_io0 vss_ df nc vss_ df vss_ df df_io7 y aa ncs1 gpio1 df _int_r nb aa ab ncs0 d f_nw e df _nre vcc_ df df_ ad dr1 nc vcc _df df _io 9 df _io3 vcc_df nll a df_ io 13 ab ac nc df _ale_n we nbe1 df_ add r0 df_ ad dr3 nc df _io 1 vcc_ mvt vcc_apps vss df_ scl k_ e vcc_df ac ad nc nc nbe0 df_ add r2 df_ io 8 df _io 2 df _io10 vss d f_io1 1 nlua rfu_ ad1 1 df _io4 ad 123456789101112 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 58 april 6, 2009 released figure 41: pxa310 processor 13mm 2 vf-bga ball map, right side 1 3 1 4 15 16 17 18 19 20 21 22 23 24 a gp io 0_2 gp i o126 gp i o115 gp i o11 6 gp i o10 7 v s s_ io 1 gp i o1 10 g pi o1 02 g pi o1 00 gp i o97 nc nc a b gpio 123 gpio119 gpi o113 g pio 99 vc c_apps vcc_ mvt gpio1 01 g pi o1 06 vc c _ s r a m vss_io1 gpio96 nc b c vss_pll vcc _apps gpio118 vcc _io1 vss gpio10 8 gpio1 04 gpio1 03 vcc _mvt gpio92 gpio94 gpio98 c d gp i o91 gp i o90 gp i o95 d e gp io 121 gp i o117 gp i o111 gp i o11 4 nc gp i o9_ 2 nc g pi o7 _2 gp i o88 gp i o87 gp i o93 e f gp io 124 gp i o122 gp i o120 gp i o10 9 gp i o10 5 g p io 10_2 gp i o8 _2 gp io 84 gp i o85 gp i o83 v cc_i o1 f g gpio75 vss_msl gpio82 gpio81 gpio89 g h vss vss vcc _apps gpio11 2 vss gpio71 vcc _msl gpio77 gpio80 gpio86 h j v s s gp io 63 gp io 79 gp i o74 gp i o76 gp i o78 j k vc c_apps vc c_lcd gpio69 gpio66 gpio72 gpio73 k l v s s gp io 60 gp io 68 gp i o65 gp i o67 gp i o70 l m v s s gp io 59 v s s_ lcd gp i o61 gp i o62 gp i o64 m n ulpi_dir vcc_ mvt gpio52 gpio55 gpio57 gpio51 n p ulp i _nx t gp io 58 gp io 49 gp i o47 gp i o54 gp i o56 p r vc c_a pp s gp io 48 gp io 45 vc c_ci gp i o53 gp i o50 r t gpio46 vss_ci gpio44 gpio42 vss vcc_apps t u vss vss vcc _apps vss u lpi_stp gpio39 vss_ulpi gpio38 gpio41 gpio43 u v gp io 37 gp io 35 v cc_u lp i gp i o36 gp i o40 v w df _io 12 vss_df gpi o2_2 vcc_mvt g pio 18 gpio 33 gpio 27 g pi o3 _2 gpio31 gpio32 gpi o34 w y vss_df df _io14 vss_card 1 gp i o8 g p io 15 gp i o4_ 2 gp i o6 _2 g pi o5 _2 gp i o21 gp i o28 gp i o29 y aa gp i o30 gp i o25 gp i o26 aa ab vcc_d f gpio3 gpio5 vc c_apps gpio7 gpio10 gpio11 vcc_io3 gpio19 gpio23 gpio20 vss_io3 ab ac df_n cs1 gpio4 vcc_card 1 vss vss vss_card 2 gp io 13 gp io 12 gp i o17 v cc_ pl l gp i o22 nc ac ad df_io 5 df_ io 6 df _io15 gpio9 g pio6 vcc_card 2 gpio16 gpio14 vss_pll gpio24 nc nc ad 1 3 1 4 15 16 17 18 19 20 21 22 23 24 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 59 4.1.2.2 pxa311 and pxa312 15mm 2 multi-chip package (mcp) and package on package (pop) bottom ball map. figure 42 and figure 43 show the bottom ball map for the pxa31x processor 15mm 2 mcp and pop packages. the balls highlighted in yellow have different functionality on the pxa30x processor. figure 42: pxa31x processor 15mm 2 mcp and package-on-package (pop, bottom) ball map , left side 123 456 78 91011 a vss vss rfu_a3 rfu_a4 rfu_a5 ntrst pwr _cap0 txtal _in vss vc c_apps gpio0_2 a b vss vss vcc_ bias nc rfu_b5 clk_tout ext_ wake up0 txtal_ out pxtal_in pw r_sda test b c nc vss t ms t ck nc nbatt_fau lt pwr_out vcc_ bbatt pxtal_out vss_bg clk_pout c d md 0 tdo pwr_en sys_en vcc_mem nreset vss vss_bbatt vcc_o sc1 3m vcc_bg g pio 1_2 d e md 1 m d2 tdi v cc_m v t g pi o3 _2 gp io 2_2 gp i o6_ 2 ngpio _res et vss_osc13 m vctcxo_e n vss_pll e f md 3 md4 dqs0 vss gpio5 _2 vss_mem vss_ mem pw r_cap1 nreset_o ut pwr _scl testclk f g md 5 md6 dq m0 nc vcc_mem vcc_ mem vss_ mem g pio 4_2 vcc_mvt vc c_io 1 vcc_df g h md 7 ma14 ma2 ma4 ma13 vcc_ mem vss_ mem vss vss vc c_apps vcc_apps h j ma8 nsd cs1 sdma1 0 ma15 vcc _mvt vcc_ mem vss_ mem gpio10_ 2 j k sd clk0 sdclk1 ma12 ma6 vss vcc_ mem vss_ mem gpio9_2 k l nsdcs0 ma9 ma0 nc vcc_apps vcc_ mem vss_ mem nc l m ma3 ma7 ma5 ma11 vss vcc_ mem vss_ mem nc m n rcomp_dd r rfu_n2 nsd cas ma1 vcc_apps vcc_ mem vss_ mem gpio8_2 n p nsdwe nsdras md8 nc nc vcc_ mem vss_ mem gpio7_2 vss vc c_apps vcc_apps p r md10 sdcke md9 dqs1 vss vcc_ mem vss_ mem vss vss_df vss_df vss_ df r t md12 md11 md14 dqm1 vcc _mvt vcc_ mem vss_ mem vss vcc_df vcc_ df vcc_df t u md15 md13 nc gpio1 df _nw p vcc_ mem vss_ mem df _io8 vcc_mvt df _ncs1 g pio 3 u v gpio2 nc gpio0 ncs1 vcc_mem d f_addr1 df _ale_n we df_c le_n oe df_n cs0 df _io 4 df _io7 v w ncs0 nc df_ int _rn b df_n we df_ nre d f_addr2 df_ io 2 df_io1 1 rfu_ w9 df _io13 df_io 14 w y vss_df vss_ df nbe0 df_ ad dr3 df _io9 df _io 10 vss df _io3 nlua nlla vcc _card 1 y aa vss_df vss_ df nbe1 df_ ad dr0 df _io0 d f_io1 vc c_apps vcc_ sr am vcc_ apps df_scl k_ e g pio 4 aa 123 456 78 91011 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 60 april 6, 2009 released 4.1.3 pxa30x processor ball maps 4.1.3.1 PXA300 processor 13mm 2 vf-bga ball figure 44 and figure 45 show the bottom ball map for the PXA300 processor 13mm 2 discrete package. the balls highlighted in yellow have different functionality on the pxa31x processor. figure 43: pxa31x processor 15mm 2 mcp and package-on-package (pop, bottom) ball map , right side 12 13 14 15 16 1 7 18 19 2 0 21 a gpio126 vcc_apps gpio116 vc c_apps gpio1 10 gpio102 gpio99 gpio96 vss vss a b gpio124 vss gpio120 gpio11 2 vss gpio106 gpio10 0 vcc_ sr am vss vss b c gpio127 g pio1 15 g pio 122 gpi o11 3 g pi o1 07 gpio 108 vcc_sram g pio 101 g pio9 5 gpio 98 c d vcc_pll g pio1 23 g pio 118 gpi o11 4 g pi o1 09 gpio 105 gpio10 3 nc g pio9 7 gpio 94 d e vss_pll gpio1 19 gpio117 vcc _io1 gpio86 gpio8 9 gpio91 gpio104 gpio9 3 gpio92 e f gpio125 gpio1 21 gpio111 vss_io1 gpio79 vss_msl gpio87 gpio85 gpio8 8 gpio90 f g vss_df vss_io1 vcc_mvt vcc _io1 gpio78 vcc_msl gpio81 gpio83 gpio8 2 gpio84 g h vcc _apps vss vss vcc_mvt gpio73 gpio7 4 gpio75 gpio77 gpio7 6 gpio80 h j vss vcc_mvt gpio71 gpio6 5 gpio67 gpio69 gpio7 0 gpio72 j k vcc_apps vss_l cd vcc_lcd gpio6 4 gpio68 gpio61 gpio6 3 gpio66 k l vcc_apps vss_l cd vcc_lcd gpio5 9 gpio56 gpio62 gpio5 8 gpio60 l m vcc_apps vss_l cd vcc_lcd gpio5 3 gpio55 gpio57 gpio5 2 gpio54 m n vss vcc_mvt gpio47 gpio4 9 gpio50 gpio51 vss vc c_apps n p vcc _apps vss vss vcc_ ci gpio43 gpio4 5 gpio46 vss_ ci vcc_ci gpio48 p r vss_df vss_ df vcc_mvt vss_ulpi vcc_u lpi gpio3 7 gpio39 gpio42 gpio4 1 gpio44 r t vcc_ df vc c_df vss vss_io 3 vcc_io3 g pio3 8 g pio 35 gpio40 g pio3 4 gpio 36 t u gp i o9 df _lo ckp re gpio8 df _i o12 gpio12 g pio1 9 g pio 31 gpi o33 g pio3 2 gpio 28 u v gpio5 gpio6 gpio11 gpio13 gpio16 ulpi_dir gpio20 gpio29 gpio30 gpio27 v w df_ io6 df_io5 gpio7 df_io15 vss_pll gpio1 7 gpio18 gpio21 ulpi_nxt u lpi_stp w y vss_card 1 vcc_apps g pio1 0 g pio 14 gpio15 g pio2 3 g pio 25 gpi o26 vss_io3 vss_ io 3 y aa vcc _apps vss vcc_card 2 vss_card 2 vcc _pll gpio2 2 gpio24 nc vss_io3 vss_ io3 aa 12 13 14 15 16 1 7 18 19 2 0 21 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 61 figure 44: PXA300 processor 13mm 2 vf-bga ball map, left side 123456789101112 a nc nc usbot g_ p vcc_ usb t ck clk_t out pw r _ c ap 0 nreset_o ut pxtal _in pwr_scl vcc_io1 gpio1_2 a b nc vss_usb usbotg_ n usbh 1_p t di n reset pw r_o ut vc c_osc1 3m pxtal_ou t vctcxo_e n vss_io1 clk_ pout b c vss_mem vss_mem usbh1 _n tdo pwr_en nbatt_fa ult tx ta l_ in txtal_ou t vcc_ bg vss_ osc1 3m vcc _pll g pio 127 c d md 0 vcc _me m tm s d e md 1 md 2 vc c _me m n t r s t ext_ wake up0 vss vcc_bbat t ng pio _re se t testclk vcc_apps vss e f md3 d qm0 vcc _mem vss_ mem sys_en pw r _ c ap 1 vss_bbat t vcc _mvt vss_bg pwr _sda g pio 125 f g md4 md5 dqs0 vc c_mem vss_ mem g h md7 ma2 md 6 vss_ mem vcc_ mvt vss vss vcc_apps vss test h j ma6 ma15 ma14 vc c_mem vss_ mem vss j k sdma10 ma8 ma4 vc c_mem vss_ mem vcc_apps k l sdc lk0 sd clk1 ma12 vc c_apps vss_ mem vss l m ma0 nsdcs1 nsdcs0 ma13 vss vss m n ma9 ma11 ma7 vc c_mem vss_ mem vss n p rc omp_d dr nsdras ma5 ma3 vcc_ mvt vss p r r fu_r 1 sdcke nsdw e ma1 vss_ mem vcc_apps r t md9 md8 nsdcas vc c_mem vss_ mem vss t u d qm1 md11 md10 vss vcc_ mvt vss vss vcc_apps vss vss u v md13 md12 dqs1 vc c_mem vss_mem v w gp i o0 m d14 m d15 nc df _cle_n oe nc nc nc df _ncs0 vcc_sra m nc w y gpio2 vcc _mem vss_mem vss_df vcc _df df_io0 vss_ df nc vss_ df vss_ df df_io7 y aa ncs1 gpio1 df _i nt_r nb aa ab ncs0 d f_nw e df _nre vcc_ df df_ ad dr1 nc vcc _df df _io 9 df _io3 vcc_df nll a df_ io 13 ab ac nc df _ale_n we nbe1 df_ add r0 df_ ad dr3 nc df _io 1 vcc_ mvt vcc_apps vss df_ scl k_ e vcc_df ac ad nc nc nbe0 df_ add r2 df_ io 8 df _io 2 df _io10 vss d f_io1 1 nlua rfu_ ad1 1 df _io4 ad 123456789101112 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 62 april 6, 2009 released figure 45: PXA300 processor 13mm 2 vf-bga ball map, right side 1 3 1 4 15 16 17 18 19 20 21 22 23 24 a gpio 0_2 gpio126 gpi o115 gpio11 6 gpio10 7 vss_ io 1 gpio1 10 g pi o1 02 g pio1 00 gpio97 nc nc a b gpio 123 gpio119 gpi o113 g pio 99 vc c_apps vcc_ mvt gpio1 01 g pi o1 06 vc c _ s r a m vss_io1 gpio96 nc b c vss_pll vcc _apps gpio118 vcc _io1 vss gpio10 8 gpio1 04 gpio1 03 vcc _mvt gpio92 gpio94 gpio98 c d gp i o91 gp i o90 gp i o95 d e gp io 121 gp i o117 gp i o111 gp i o11 4 nc rf u_e 18 nc r fu_e 20 gp i o88 gp i o87 gp i o93 e f gpio 124 gpio122 gpi o120 gpio10 9 gpio10 5 r fu_f 18 rfu_ f19 gpio 84 gpio85 gpio83 vcc_io1 f g gpio75 vss_msl gpio82 gpio81 gpio89 g h vss vss vcc _apps gpio11 2 vss gpio71 vcc _msl gpio77 gpio80 gpio86 h j vss gpio63 gpio79 gpio74 gpio76 gpio78 j k vc c_apps vc c_lcd gpio69 gpio66 gpio72 gpio73 k l vss gpio60 gpio68 gpio65 gpio67 gpio70 l m vss gpio59 vss_ lcd gpio61 gpio62 gpio64 m n rf u_n17 vcc_ mvt gpio 52 gpio55 gpio57 gpio51 n p rfu_p17 gpio58 gpio49 gpio47 gpio54 gpio56 p r vc c_apps gpio 48 gpio 45 vc c_ci gpio53 gpi o50 r t g pio 46 vss_ci gpio 44 gpio42 vss vcc_apps t u vss vss vcc _apps vss rf u_u17 gpio 39 vss_ io 3 gpio38 gpio41 gpi o43 u v gpio37 gpio35 vcc_io3 gpio36 gpio40 v w df _io 12 vss_df gpi o2_2 vcc_mvt g pio 18 gpio 33 gpio 27 g pi o3 _2 gpio31 gpio32 gpi o34 w y vss_df df _io14 vss_card 1 gp i o8 g p io 15 gp i o4_ 2 gp i o6 _2 g pi o5 _2 gp i o21 gp i o28 gp i o29 y aa gp i o30 gp i o25 gp i o26 aa ab vcc_d f gpio3 gpio5 vc c_apps gpio7 gpio10 gpio11 vcc_io3 gpio19 gpio23 gpio20 vss_io3 ab ac df_n cs1 gpio4 vcc_card 1 vss vss vss_card 2 gp io 13 gp io 1 2 gp i o17 v c c _ pl l gp i o22 n c ac ad df_io 5 df_ io 6 df _io15 gpio9 g pio6 vcc_card 2 gpio16 gpio14 vss_pll gpio24 nc nc ad 1 3 1 4 15 16 17 18 19 20 21 22 23 24 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 63 4.1.4 pxa30x processor and pxa302 processor 15mm 2 multi-chip package (mcp) and package on package (pop) bottom ball map figure 46 and figure 47 show the bottom ball map for the pxa30x processor 15mm 2 mcp and pop packages.the balls highlighted in yellow have different functionality on the pxa31x processor. figure 46: pxa30x 15mm 2 mcp and package-on-package (pop) bottom ball map , left side 1 234 567 891011 a vss_u sb vss_usb usbotg_n usbotg_p usbh1_ n ntrst pw r_cap0 txtal_in vss vcc_apps gpio0_2 a b vss_u sb vss_usb vcc_u sb nc u sbh1_ p clk_t out ext_wake up0 txtal_ou t pxtal_ in pwr _sd a test b c nc vss tms t ck nc nbatt_fau lt pw r_o ut vc c_bbat t pxtal_o ut vss_bg c lk_pout c d md0 tdo pw r_en sys_en vcc_ mem nr eset vss vss_ bbatt vcc_ osc1 3m vcc_ bg gpio 1_2 d e md1 md2 t di vcc _mvt g pio 3_2 gpi o2_ 2 g pi o6 _2 ngpio_r es et vss_ osc13 m vctcxo_e n vss_pll e f md3 md4 dqs0 vss gpio5_2 vss_ mem vss_mem pw r_c ap1 n reset_o ut pw r_scl testcl k f g md5 md6 dqm0 nc vcc_ mem vc c_mem vss_mem gpio 4_2 vcc_mvt vcc_io1 vcc_df g h m d 7 m a1 4 m a2 m a 4 m a 1 3 vc c _ m em v s s _ m em v ss v s s v c c _ a p p s v c c _ ap p s h j ma8 nsdcs1 sdma10 ma15 vcc_mvt vc c_mem vss_mem rfu_j8 j k sdclk0 sdcl k1 ma12 ma6 vss vc c_mem vss_mem rfu_ k8 k l n sd c s0 ma 9 m a0 n c v c c _ a p p s vc c _ m em v s s _ m em n c l m ma3 ma7 ma5 ma11 vss vc c_mem vss_mem n c m n rcomp_dd r rfu_n2 nsdcas ma1 vcc_apps vc c_mem vss_mem rfu_n8 n p nsdw e nsd ras md 8 nc nc vc c_mem vss_mem rfu_ p8 vss vcc_apps vcc_ apps p r md10 sdc ke md 9 dqs1 vss vc c_mem vss_mem vss vss_df vss_ df vss_df r t md12 md 11 md14 dqm1 vcc_mvt vc c_mem vss_mem vss vcc_ df vcc_df vcc_df t u m d15 md 13 nc g pio 1 df _nw p vc c_m em vss_m em d f_i o8 vcc_mvt df _ncs1 gpio3 u v gpio2 nc gpio0 ncs1 vcc_mem df_addr1 df_ ale_n we df _cle_n oe df_ncs0 df_io4 d f_io7 v w ncs0 nc df _in t_rn b df _nw e df _nre df_ add r2 df _io2 df _io 11 rf u_w 9 df_io1 3 df _io 14 w y vss_ df vss_df nbe0 df_a ddr3 d f_io9 df _io10 vss d f_io3 nl ua nll a vcc_card 1 y aa vss_ df vss_df nbe1 df_a ddr0 d f_io0 df_ io 1 vcc_apps vcc_sram vc c_apps df _sc lk_e gpio4 aa 1 234 567 891011 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 64 april 6, 2009 released 4.1.5 pxa303 processor 19mm 2 vf-bga ball figure 48 and figure 49 show the bottom ball map for the pxa303 processor 19mm 2 discrete package. figure 47: pxa30x processor 15mm 2 mcp and package-on-package (pop, bottom) ball map , right side 12 13 14 15 16 17 18 1 9 20 21 a gpio1 26 vcc_apps gpio116 vcc_apps gpio110 gpio10 2 gpio99 gpio9 6 vss vss a b g pi o1 24 vss gpi o120 g pio1 12 vss gpio10 6 g pio1 00 vcc_sram vss vss b c g pi o1 27 g pio 115 gpi o122 g pio1 13 g pio 107 gpio10 8 vcc_ sram gpio 101 g pio 95 gpi o98 c d vcc_ pl l g pio 123 gpi o118 g pio1 14 g pio 109 gpio10 5 g pio1 03 n c g pio 97 gpi o94 d e vss_pll gpio119 gpio117 vcc_io1 gpio8 6 gpio89 gpio91 gpio104 gpio93 gpio92 e f g pi o1 25 g pio 121 gpi o111 vss_io 1 g pi o7 9 vss_m sl gpi o87 g pi o8 5 g pio 88 gpi o90 f g vss_ df vss_io1 vcc_mvt vcc_io1 gpio7 8 vcc_ msl gpio81 gpio8 3 gpio82 gpio84 g h vcc_apps vss vss vcc _mvt gpio7 3 gpio74 gpio75 gpio7 7 gpio76 gpio80 h j v s s vcc _mv t g pi o7 1 g p io 65 gp i o67 g pi o6 9 g p io 70 gp i o72 j k vcc _apps vss_ lcd vcc_l cd gpio64 gpio68 gpio6 1 gpio63 gpio66 k l vcc _apps vss_ lcd vcc_l cd gpio59 gpio56 gpio6 2 gpio58 gpio60 l m vcc _apps vss_ lcd vcc_l cd gpio53 gpio55 gpio5 7 gpio52 gpio54 m n vss vcc _mvt gpio4 7 gpio49 gpio50 gpio5 1 vss vcc_apps n p vcc_apps vss vss vcc _ci gpio4 3 gpio45 gpio46 vss_ci vcc_ ci gpio48 p r vss_ df vss_df vcc_mvt rfu_r1 5 rfu_ r16 gpio37 gpio39 gpio4 2 gpio41 gpio44 r t vc c_df vcc_df vss vss_io 3 vcc_io 3 g pio 38 gpio35 g pio4 0 g pio 34 gpio36 t u g p io 9 nc gp i o8 d f_i o1 2 g pi o1 2 g p io 19 gp i o31 g pi o3 3 g p io 32 gp i o28 u v gpio5 gpio6 gpio11 gpio13 gpio16 rfu_v17 gpio20 gpio29 gpio30 gpio27 v w df _io 6 df _i o5 gpio7 d f_io1 5 vss_ pl l g pio 17 gpi o18 g pi o2 1 rf u_w 20 rfu_ w2 1 w y vss_card 1 vcc_apps gpio10 gpio14 gpio1 5 gpio23 gpio25 gpio2 6 vss_io3 vss_io3 y aa vcc_apps vss vcc_card 2 vss_card 2 vcc_pll gpio22 gpio24 n c vss_io3 vss_io3 aa 12 13 14 15 16 17 18 1 9 20 21 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 65 figure 48: pxa303 processor 19mm 2 vf-bga ball map, left side 1 23456789101112 a nc nc usbh1 _n usbh 1_p nbatt_fa ult pw r _ c ap 0 ng pio _re se t vc c_osc1 3m pw r_scl test g pi o 1_2 g pio 127 a b nc nc usbot g_ p vcc_ usb sys_en pw r_o ut vss_bbat t pxt al _in vcc_ bg t est clk vcc_io1 g pio 0_2 b c md 2 md 1 usbotg_ n vss_usb ntrst vss txtal_ou t pxtal_ou t vss_ osc1 3m pwr_ sd a clk_po ut g pio 126 c d vcc_ mem dq s0 md 0 tms tdo clk_t out vcc_bbat t tx t al _in nreset _o ut vcc _mvt vss_bg vss_io1 d e md5 vss_mem dqm0 pw r_en tdi tck ext_ wake up0 nreset pwr_ cap 1 vss vcc_apps vctcxo_e n e f md7 md6 md 4 vss_ mem vss_ mem f g ma14 ma15 vcc _mem md 3 vc c_mem g h ma8 ma6 ma4 vss_ mem vcc_mvt h j vcc_ mem vss_mem ma12 ma2 vss vss vss vss vss j k nsdcs0 nsdcs1 sd clk0 sdclk1 sdma10 vss vss vss vss k l ma13 ma11 ma0 vc c_apps vss vss vss vss vss l m ma5 ma7 ma9 vss_ mem vc c_mem vss vss vss vss m n ma1 nsdras nsdcas ma3 rcomp_d dr vss vss vss vss n p nsdwe sdcke vcc_mvt rfu vss_ mem vss vss vss vss p r md8 md9 md10 md11 vc c_mem vss vss vss vss r t d qm1 dqs1 md12 vss_mem vc c_mem t u md13 md14 md15 vss_ mem ncs1 u v gpio0 gpio1 gpio2 vcc_ df vss_df v w ncs0 df _in t_r nb df_n we d f_nre n be0 vcc _df vss_d f vc c_df vcc_apps nc vss_ df vss w y df_addr 2 df_addr 1 df _ale_n we n be1 df_ ad dr0 df _ad dr3 df _io 9 d f_io1 0 vc c _ s r a m vss vcc_df vcc_apps y aa df_io 0 df_ io 8 df_ io 1 df_ io 2 nc vss vcc_ mvt n lua df_scl k_ e df _io6 g pio 3 vc c_card 1 aa ab nc nc df _cle_n oe df _io11 df_ io 3 df _ncs0 nlla d f_io1 2 df _io7 df _ncs1 g pio 5 vss_ car d 1 ab ac nc nc df_ io 4 df_ io 5 df _io13 df _io14 df _io15 g pio 4 g pio 6 g pio 7 g pio 9 gpio10 ac 1 23456789101112 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 66 april 6, 2009 released figure 49: pxa303 processor 19mm 2 vf-bga ball map, right side 1 3 1 4 15 16 17 18 19 20 21 22 23 a gp io 125 gp i o122 gp i o120 gp i o11 5 gp i o11 2 gp i o10 9 gp i o1 06 g pi o1 02 g pi o1 01 nc nc a b gp io 124 gp i o121 gp i o117 gp i o11 4 gp i o11 0 gp i o10 8 gp i o1 03 g pi o1 00 rfu_ b2 1 nc nc b c v cc_p ll gp i o118 gp i o116 gp i o11 1 gp i o10 7 gp i o10 5 rf u_c1 9 rf u_c2 0 gp i o97 gp i o96 gp i o93 c d vss_pll gpio123 gpio119 vss_io1 gpio10 4 rfu_d18 vc c _ s r a m gp io 98 gp i o95 gp i o92 gp i o90 d e vss vcc _apps gpio113 vcc _io 1 vcc_m vt gpio 99 vss_ io 1 gpio 94 gpio91 gpio87 gpi o86 e f vcc_io1 gpio89 gpio88 gpio85 gpio83 f g vss vcc_ mvt gpio84 gpio81 gpio80 g h vss_msl vcc _msl gpio82 gpio78 gpio77 h j v ss v s s v s s gp io 75 gp io 79 gp i o76 gp i o74 gp i o73 j k vss vss vss vc c_lcd vss_ lcd gpio71 gpio72 gpio70 k l v ss v s s v s s gp io 69 gp io 67 gp i o65 gp i o68 gp i o66 l m vss vss vss vc c_lcd vss_ lcd gpio63 gpio64 gpio62 m n v ss v s s v s s gp io 57 gp io 54 gp i o59 gp i o60 gp i o61 n p vss vss vss vcc_ mvt gpio52 gpio55 gpio56 gpio58 p r vss vss vss vcc_ ci vcc_apps gpio50 gpio51 gpio53 r t v ss _ci gp io 41 gp i o47 gp i o48 gp i o49 t u gp io 27 v s s_ io 3 gp i o44 gp i o45 gp i o46 u v nc nc gp i o36 gp i o42 gp i o43 v w vcc_ apps vcc_mvt vss_pll vcc_pll gpio25 gpio6_ 2 nc gpio30 vcc_io3 gpio39 gpio40 w y vss vcc_card 2 g p io 15 g p io 19 g p io 24 gp i o4_ 2 nc nc gp i o31 gp i o37 gp i o38 y aa gp i o8 vss_card 1 g p io 16 vcc _io 3 g p io 23 gp i o3_ 2 nc nc gp i o33 gp i o34 gp i o35 aa ab gpio11 gpio13 gpio18 vss_io3 gpio22 gpio2_ 2 nc nc gpio32 nc nc ab ac g pio 12 g pio 14 g pio 17 g pio 20 g pio 21 gpio 26 gpi o5 _2 gpio 28 gpio29 nc nc ac 1 3 1 4 15 16 17 18 19 20 21 22 23 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 67 4.1.6 pxa312 and pxa302 package on package (pop) top ball maps 4.1.6.1 pxa312 and pxa302 processor 15mm 2 package-on-package (pop) top ball map figure 50: pxa302 processor and pxa312 processor pop top ball map, left side 1234567891011 a nc vss_ mem nc vss_ df nc nc nc nc vss_df df_ cle_n oe nc a b vss_ mem vcc_mem nc vc c_df nc nc nc nc vcc_df df _ale_n we nc b c df_ nwe df _int_ r nb c d md1 md0 d e vss_ mem vcc_mem e f md3 md2 f g md5 md4 g h vss_ mem vcc_mem h j md7 md6 j k dqm0 dq s0 k l dqm1 dq s1 l m vss_ mem vcc_mem m n md9 md8 n p vss_ mem vcc_mem p r md11 md10 r t md13 md12 t u vss_ mem vcc_mem u v md15 md14 v w sdcke sdclk0 w y nc sdclk1 y aa nc vss_d f vc c_df df _io0 vcc_df df _io2 df _io4 vcc_df df _io6 nc df _sclk_ e aa ab nc vcc_mem vss_df df_io1 vss_df df_io3 df_io5 vss_df df_io7 nc nc ab 1234567891011 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 68 april 6, 2009 released 4.2 pin use tables these tables include the ball number, ball name, and type for each of pins. see ta bl e 1 2 to decode the pin ?type?. also included is the state of each pin with respect to reset and power modes. additionally, at the beginning of each group of pins is the power domain that powers all the pins in that group. for example, the vcc_batt group of pins in table 11 starts with ball c6 and ends with c8. the next group of pins are on the vcc_io1 domain. figure 51: pxa302 processor and pxa312 processor pop top ball map, right side note: the df_nwp signal is used as a write-protect pin for packages that use nand devices (f22) and as a reset signal for packages that use a static memory controller (smc) device on gpio1 (ncs2) (c21). the df_nwp signal on the bottom package must be connected to either an external reset circuit or tied accordingly for write protection of the nand device. when making connections to the df_nwp pin, hardware must ensure the proper voltage levels are used for the voltage requirements on the top package. for example, when connecting nreset_out (3v) to df_nwp as a reset for a onenand device (1.8v), a level shifter must be used to reduce the voltage. 12 13 14 15 16 17 18 19 20 21 22 a nc nc nc vss_df nc nc nc nc nc vss_df nc a b nc nc nc vcc_df nc nc nc nc vcc_df vcc_df vss_df b c df_nwp nc c d gpio1 gpio2 d e df_ncs0 df_ncs1 e f df_nre df_nwp f g df_ale_ nwe nc g h nsdwe df_cle_ noe h j vcc_me m vss_me m j k ma0 ma1 k l ma2 ma3 l m ma4 ma5 m n ma6 ma7 n p ma14 ma15 p r nsdcs0 nsdcs1 r t nsdras nsdcas t u ma8 ma9 u v s d m a 10 m a 11 v w ma12 ma13 w y nc vss_me m y aa vcc_df nc df_io8 vcc_df df_io10 df_io12 vcc_df df_io14 nlla vcc_me m nc aa ab v ss_df nc df_ io9 v ss_ df df_ io11 df_ io13 v ss_ df df_ io15 nc v cc_ df nc ab 12 13 14 15 16 17 18 19 20 21 22 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 69 each multi-function pin (mfp) signal alternate function inputs and outputs are shown in the pxa3xx processor family vol. i: system and timer configuration developers manual , ?pin description and control? chapter. 4.2.1 pxa32x processor pin use table 9 lists the mapping of signals to specific pxa32x processor package pins. table 9: pxa32x processor pin usage summary 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode vcc_bbatt c6 c6 clk_tout clk_tout oc clk-out 44 h8 g5 ext_wakeup0 ext_wakeup0 icocz pd-0 11 pd-0 11 pd-0 11 h6 f5 ext_wakeup1 ext_wakeup1 icocz pu-1 11 pu-1 11 pu-1 11 e9 b7 nbatt_fault nbatt_fault ic input input input d7 a11 ngpio_reset ngpio_reset ic pu-1 11 pu-1 11 pu-1 11 b7 e6 nreset nreset ic input 7 input input g9 c9 nreset_out nreset_out oc low 12 12 f7 d6 ntrst ntrst ic input 7 input 7 input 7 b8 d7 pwr_cap0 pwr_cap0 oa - - - g8 c7 pwr_cap1 pwr_cap1 oa - - - a6 a7 pwr_en pwr_en oc low low low c7 b8 pwr_out pwr_out oa - - - g7 e5 sys_en sys_en oc low low high e4 b4 tck tck ic input input input a5 b6 tdi tdi ic input 7 input 7 input 7 f6 d5 tdo tdo ocz hi-z hi-z hi-z e7 a8 tms tms ic input 7 input 7 input 7 a7 d8 txtal_in txtal_in ia 222 a8 c8 txtal_out txtal_out oa 222 vcc_mvt f9 b10 pxtal_in pxtal_in ia 222 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 70 april 6, 2009 released e10 c10 pxtal_out pxtal_out oa 222 vcc_io1 d9 d11 clk_pout clk_pout oc low float low h12 b18 gpio113 gpio113 icocz pd-0 1 float 1 3 b14 a17 gpio114 gpio114 icocz pd-0 1 float 1 3 h13 c17 gpio115 gpio115 icocz pd-0 1 float 1 3 a15 d17 gpio116 gpio116 icocz pd-0 1 float 1 3 g14 e16 gpio117 gpio117 icocz pd-0 1 float 1 3 b13 c16 gpio118 gpio118 icocz pd-0 1 float 1 3 k8 b17 gpio119 gpio119 icocz pd-0 1 float 1 3 a14 e14 gpio120 gpio120 icocz pd-0 1 float 1 3 d12 b16 gpio121 gpio121 icocz pd-0 1 float 1 3 b12 c15 gpio122 gpio122 icocz pd-0 1 float 1 3 g13 a16 gpio123 gpio123 icocz pd-0 1 float 1 3 c13 d14 gpio124 gpio124 icocz pd-0 1 float 1 3 e13 e13 gpio125 gpio125 icocz pd-0 1 float 1 3 a13 a15 gpio126 gpio126 icocz pd-0 1 ]float 1 3 h10 d13 gpio127 gpio127 icocz pd-0 1 float 1 3 a12 e12 gpio0_2 gpio0_2 icocz pu-1 1 float 1 3 g11 b14 gpio1_2 gpio1_2 icocz pu-1 1 float 1 3 c11 c13 gpio2_2 gpio2_2 icocz pd-0 1 float 1 3 f13 a14 gpio3_2 gpio3_2 icocz pd-0 1 float 1 3 a11 b13 gpio4_2 gpio4_2 icocz pd-0 1 float 1 3 e11 d12 gpio5_2 gpio5_2 icocz pd-0 1 float 1 3 h11 c11 pwr_scl pwr_scl icocz pu-1 11 pu-1 11 float 1 a10 a12 pwr_sda pwr_sda icocz pu-1 11 pu-1 11 float 1 d10 a13 test test ic input 5 input 5 input 5 g12 c12 testclk testclk ic input 5 input 5 input 5 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 71 f11 b12 vctcxo_en vctcxo_en oc low float low vcc_df w7 ac8 df_addr0 df_addr0 ocz pd-0 1 float 1 3 w8 ad8 df_addr1 df_addr1 ocz pd-0 1 float 1 3 v8 af8 df_addr2 df_addr2 ocz pd-0 1 float 1 3 y8 ae9 df_addr3 df_addr3 ocz pd-0 1 float 1 3 w1 ae5 df_int_rnb df_rnb icz pu-1 1 float 1 3 u9 ad9 df_io0 df_io0 icocz pd-0 1 float 1 3 p6 ac11 df_io1 df_io1 icocz pd-0 1 float 1 3 u7 ad10 df_io2 df_io2 icocz pd-0 1 float 1 3 t10 af10 df_io3 df_io3 icocz pd-0 1 float 1 3 t9 ac12 df_io4 df_io4 icocz pd-0 1 float 1 3 u10 af12 df_io5 df_io5 icocz pd-0 1 float 1 3 v10 ae12 df_io6 df_io6 icocz pd-0 1 float 1 3 w10 af13 df_io7 df_io7 icocz pd-0 1 float 1 3 v9 ab10 df_io8 df_io8 icocz pd-0 1 float 1 3 v11 af9 df_io9 df_io9 icocz pd-0 1 float 1 3 r13 ae10 df_io10 df_io10 icocz pd-0 1 float 1 3 y9 ad11 df_io11 df_io11 icocz pd-0 1 float 1 3 t11 ab13 df_io12 df_io12 icocz pd-0 1 float 1 3 t14 ad12 df_io13 df_io13 icocz pd-0 1 float 1 3 r8 ab14 df_io14 df_io14 icocz pd-0 1 float 1 3 p10 ac13 df_io15 df_io15 icocz pd-0 1 float 1 3 d8 af3 df_ale_nwe1 df_ale ocz pu-1 1 float 1 3 t7 ab6 df_ale_nwe2 df_ale ocz pu-1 1 float 1 3 p8 ae6 df_ncs0 df_ncs0 ocz pu-1 1 float 1 3 b5 af6 df_ncs1 df_ncs1 ocz pu-1 1 float 1 3 u6 ad7 df_nre df_noe ocz pu-1 1 float 1 3 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 72 april 6, 2009 released t8 af7 df_nwe df_nwe ocz pu-1 1 float 1 3 w5 af4 df_sclk_e df_sclk_e ocz pd-0 1 float 1 3 v3 ac2 gpio2 gpio2 icocz pd-0 1 float 1 3 r6 ad2 gpio3 gpio3 icocz pu-1 1 float 1 3 m8 ad3 gpio4 gpio4 icocz pu-1 1 float 1 3 p11 af14 gpio5 gpio5 icocz pu-1 1 float 1 3 w12 ae14 gpio6 gpio6 icocz pu-1 1 float 1 3 r10 ab15 gpio7 gpio7 icocz pu-1 1 float 1 3 aa12 ac15 gpio8 gpio8 icocz pu-1 1 float 1 3 t6 ae4 nbe0 nbe0 ocz pu-1 1 float 1 3 y6 af5 nbe1 nbe1 ocz pu-1 1 float 1 3 c10 ad5 df_cle_noe nd_cle ocz pu-1 1 float 1 3 aa8 ae8 nlla nlla ocz pu-1 1 float 1 3 u8 ae7 nlua nlua ocz pu-1 1 float 1 3 v5 ae3 nxcvren nxcvren ocz pu-1 1 float 1 3 vcc_io3 p12 af16 gpio9 gpio9 icocz pu-1 1 float 1 3 v13 ab16 gpio11 gpio11 icocz pd-0 1 float 1 3 u13 ab17 gpio12 gpio12 icocz pd-0 1 float 1 3 y13 af17 gpio13 gpio13 icocz pd-0 1 float 1 3 p13 ac17 gpio14 gpio14 icocz pu-1 1 float 1 3 y14 af19 gpio15 gpio15 icocz pu-1 1 float 1 3 t13 ab19 gpio16 gpio16 icocz pu-1 1 float 1 3 u14 ac19 gpio17 gpio17 icocz pu-1 1 float 1 3 vcc_io4 p14 w25 gpio10 gpio10 icocz pd-0 1 float 1 3 u20 ac23 gpio30 gpio30 icocz pd-0 1 float 1 3 u12 ad24 gpio31 gpio31 icocz pd-0 1 float 1 3 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 73 v20 aa22 gpio32 gpio32 icocz pu-1 1 float 1 3 v18 ad25 gpio33 gpio33 icocz pu-1 1 float 1 3 t18 ac24 gpio34 gpio34 icocz pd-0 1 float 1 3 u17 ad26 gpio35 gpio35 icocz pd-0 1 float 1 3 t17 ac25 gpio36 gpio36 icocz pd-0 1 float 1 3 t16 ab25 gpio37 gpio37 icocz pd-0 1 float 1 3 t20 ac26 gpio38 gpio38 icocz pd-0 1 float 1 3 t15 y22 gpio39 gpio39 icocz pd-0 1 float 1 3 t19 aa23 gpio40 gpio40 icocz pu-1 1 float 1 3 r16 y23 gpio41 gpio41 icocz pd-0 1 float 1 3 r20 aa24 gpio42 gpio42 icocz pd-0 1 float 1 3 r15 w22 gpio43 gpio43 icocz pu-1 1 float 1 3 r19 aa25 gpio44 gpio44 icocz pu-1 1 float 1 3 p16 w24 gpio45 gpio45 icocz pu-1 1 float 1 3 r18 y26 gpio46 gpio46 icocz pu-1 1 float 1 3 p18 y25 gpio47 gpio47 icocz pu-1 1 float 1 3 p20 v22 gpio48 gpio48 icocz pu-1 1 float 1 3 vcc_ci p19 w26 gpio49 gpio49 icocz pd-0 1 float 1 3 p15 v23 gpio50 gpio50 icocz pd-0 1 float 1 3 r21 u22 gpio51 gpio51 icocz pd-0 1 float 1 3 m14 u23 gpio52 gpio52 icocz pd-0 1 float 1 3 m18 t22 gpio53 gpio53 icocz pd-0 1 float 1 3 m17 u25 gpio54 gpio54 icocz pd-0 1 float 1 3 n19 u26 gpio55 gpio55 icocz pd-0 1 float 1 3 m16 t24 gpio56 cif_dd7 icocz pd-0 1 float 1 3 m19 r22 gpio57 gpio57 icocz pd-0 1 float 1 3 n17 t23 gpio58 gpio58 icocz pd-0 1 float 1 3 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 74 april 6, 2009 released m20 r24 gpio59 cif_mclk icocz pd-0 1 float 1 3 l15 r23 gpio60 cif_pclk icz pd-0 1 float 1 3 k21 p24 gpio61 cif_hsync icocz pd-0 1 float 1 3 l16 p26 gpio62 cif_vsync icocz pd-0 1 float 1 3 vcc_io6 g18 f22 gpio83 gpio83 icocz pd-0 1 float 1 3 f16 d26 gpio84 gpio84 icocz pd-0 1 float 1 3 f18 e23 gpio85 gpio85 icocz pd-0 1 float 1 3 f17 e24 gpio86 gpio86 icocz pd-0 1 float 1 3 d20 d22 gpio87 gpio87 icocz pu-1 1 float 1 3 d16 c25 gpio88 gpio88 icocz pu-1 1 float 1 3 f19 d25 gpio89 gpio89 icocz pu-1 1 float 1 3 d17 c26 gpio90 gpio90 icocz pu-1 1 float 1 3 e18 d24 gpio91 gpio91 icocz pd-0 1 float 1 3 e21 d23 gpio92 gpio92 icocz pd-0 1 float 1 3 e20 d21 gpio93 gpio93 icocz pd-0 1 float 1 3 e16 b23 gpio94 gpio94 icocz pd-0 1 float 1 3 c21 c23 gpio95 gpio95 icocz pd-0 1 float 1 3 d21 c24 gpio96 gpio96 icocz pd-0 1 float 1 3 d19 b25 gpio97 gpio97 icocz pd-0 1 float 1 3 k14 b24 gpio98 gpio98 icocz pd-0 1 float 1 3 c18 a24 gpio99 gpio99 icocz pu-1 1 float 1 3 c17 a23 gpio100 gpio100 icocz pu-1 1 float 1 3 d18 a22 gpio101 gpio101 icocz pu-1 1 float 1 3 b18 a21 gpio102 gpio102 icocz pu-1 1 float 1 3 c19 b21 gpio103 gpio103 icocz pu-1 1 float 1 3 a18 e22 gpio104 gpio104 icocz pu-1 1 float 1 3 c16 c21 gpio105 gpio105 icocz pu-1 1 float 1 3 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 75 b19 a20 gpio106 gpio106 icocz pu-1 1 float 1 3 d15 b20 gpio107 gpio107 icocz pd-0 1 float 1 3 a17 e21 gpio108 gpio108 icocz pd-0 1 float 1 3 r9 a19 gpio109 gpio109 icocz pu-1 1 float 1 3 b16 b19 gpio110 gpio110 icocz pd-0 1 float 1 3 r7 e19 gpio111 gpio111 icocz pd-0 1 float 1 3 c15 c19 gpio112 gpio112 icocz pu-1 1 float 1 3 vcc_lcd k19 m24 gpio63 gpio63 icocz pu-1 1 float 1 3 k17 l25 gpio64 gpio64 icocz pd-0 1 float 1 3 j18 m26 gpio65 gpio65 icocz pd-0 1 float 1 3 j17 k22 gpio66 gpio66 icocz pd-0 1 float 1 3 j19 l24 gpio67 gpio67 icocz pd-0 1 float 1 3 j15 l26 gpio68 gpio68 icocz pd-0 1 float 1 3 j20 l23 gpio69 gpio69 icocz pd-0 1 float 1 3 j14 k26 gpio70 gpio70 icocz pd-0 1 float 1 3 h20 k23 gpio71 gpio71 icocz pd-0 1 float 1 3 j16 k24 gpio72 gpio72 icocz pd-0 1 float 1 3 h18 j22 gpio73 gpio73 icocz pu-1 1 float 1 3 h17 j23 gpio74 gpio74 icocz pd-0 1 float 1 3 n20 p25 gpio6_2 gpio6_2 icocz pd-0 1 float 1 3 l14 p23 gpio7_2 gpio7_2 icocz pd-0 1 float 1 3 l20 n23 gpio8_2 gpio8_2 icocz pd-0 1 float 1 3 k15 m22 gpio9_2 gpio9_2 icocz pd-0 1 float 1 3 l19 n25 gpio10_2 gpio10_2 icocz pd-0 1 float 1 3 l18 l22 gpio11_2 gpio11_2 icocz pd-0 1 float 1 3 l21 n26 gpio12_2 gpio12_2 icocz pd-0 1 float 1 3 l17 m25 gpio13_2 gpio13_2 icocz pd-0 1 float 1 3 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 76 april 6, 2009 released h16 k25 gpio14_2 gpio14_2 icocz pd-0 1 float 1 3 h21 h22 gpio15_2 gpio15_2 icocz pd-0 1 float 1 3 h15 j24 gpio16_2 gpio16_2 icocz pd-0 1 float 1 3 h19 h25 gpio17_2 gpio17_2 icocz pd-0 1 float 1 3 vcc_mem k1 c3 dqm0 dqm0 oc high high high h2 f1 dqm1 dqm1 oc high high high t3 v2 dqm2 dqm2 oc high high high w4 aa3 dqm3 dqm3 oc high high high j2 d2 dqs0 dqs0 isocz pd-0 pd-0 pd-0 m2 e1 dqs1 dqs1 isocz pd-0 pd-0 pd-0 aa10 w2 dqs2 dqs2 isocz pd-0 pd-0 pd-0 aa11 aa2 dqs3 dqs3 isocz pd-0 pd-0 pd-0 u3 ac4 gpio0 gpio0 icocz pd-0 1 pd-0 1 3 v4 ac3 gpio1 gpio1 icocz pd-0 1 pd-0 1 3 j8 k4 ma0 ma0 oc high high high j3 j1 ma1 ma1 oc high high high f5 j2 ma2 ma2 oc high high high g4 h1 ma3 ma3 oc high high high k7 t4 ma4 ma4 oc high high high m21 p1 ma5 ma5 oc high high high k6 r3 ma6 ma6 oc high high high n21 p3 ma7 ma7 oc high high high v21 n3 ma8 ma8 oc high high high u21 p2 ma9 ma9 oc high high high l2 p4 ma11 ma11 oc high high high j6 l3 ma12 ma12 oc high high high n8 l2 ma13 ma13 oc high high high table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 77 j4 k1 ma14 ma14 oc high high high n18 l4 ma15 ma15 oc high high high d2 b3 md0 md0 icsocz pd-0 pd-0 pd-0 c2 b2 md1 md1 icsocz pd-0 pd-0 pd-0 e2 c2 md2 md2 icsocz pd-0 pd-0 pd-0 e1 c4 md3 md3 icsocz pd-0 pd-0 pd-0 f2 c1 md4 md4 icsocz pd-0 pd-0 pd-0 f1 d3 md5 md5 icsocz pd-0 pd-0 pd-0 j1 e2 md6 md6 icsocz pd-0 pd-0 pd-0 g3 d1 md7 md7 icsocz pd-0 pd-0 pd-0 r2 e3 md8 md8 icsocz pd-0 pd-0 pd-0 g5 f3 md9 md9 icsocz pd-0 pd-0 pd-0 n1 f2 md10 md10 icsocz pd-0 pd-0 pd-0 g6 g3 md11 md11 icsocz pd-0 pd-0 pd-0 t2 h3 md12 md12 icsocz pd-0 pd-0 pd-0 h5 g2 md13 md13 icsocz pd-0 pd-0 pd-0 w2 g1 md14 md14 icsocz pd-0 pd-0 pd-0 h4 h2 md15 md15 icsocz pd-0 pd-0 pd-0 y3 v4 md16 md16 icsocz pd-0 pd-0 pd-0 n5 v3 md17 md17 icsocz pd-0 pd-0 pd-0 y5 v1 md18 md18 icsocz pd-0 pd-0 pd-0 aa4 w1 md19 md19 icsocz pd-0 pd-0 pd-0 aa6 y1 md20 md20 icsocz pd-0 pd-0 pd-0 aa7 aa1 md21 md21 icsocz pd-0 pd-0 pd-0 w3 y3 md22 md22 icsocz pd-0 pd-0 pd-0 aa9 w3 md23 md23 icsocz pd-0 pd-0 pd-0 r3 y2 md24 md24 icsocz pd-0 pd-0 pd-0 y11 aa4 md25 md25 icsocz pd-0 pd-0 pd-0 table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 78 april 6, 2009 released y4 ab1 md26 md26 icsocz pd-0 pd-0 pd-0 w9 ab4 md27 md27 icsocz pd-0 pd-0 pd-0 u4 ac1 md28 md28 icsocz pd-0 pd-0 pd-0 t4 ad1 md29 md29 icsocz pd-0 pd-0 pd-0 aa5 ab3 md30 md30 icsocz pd-0 pd-0 pd-0 u5 ab2 md31 md31 icsocz pd-0 pd-0 pd-0 t21 r4 nsdcas nsdcas oc high high high k4 l1 nsdcs0 nsdcs0 oc high high high j7 n4 nsdcs1 nsdcs1 oc high high high l4 n2 nsdras nsdras oc high high high h3 m3 nsdwe nsdwe oc high high high l1 r1 rcomp_ddr rcomp_ddr oa - - - u2 m2 sdcke sdcke oc low low low y2 m1 sdclk0 sdclk0 oc low low low m6 n1 sdclk1 sdclk1 oc high high high k3 k2 sdma10 sdma10 oc high high high vcc_msl f20 h23 gpio75 gpio75 icocz pd-0 1 float 1 3 g15 h24 gpio76 gpio76 icocz pd-0 1 float 1 3 g21 g24 gpio77 gpio77 icocz pd-0 1 float 1 3 g16 g22 gpio78 gpio78 icocz pd-0 1 float 1 3 f21 f25 gpio79 gpio79 icocz pd-0 1 float 1 3 h14 f23 gpio80 gpio80 icocz pd-0 1 float 1 3 g20 e25 gpio81 gpio81 icocz pd-0 1 float 1 3 k16 e26 gpio82 gpio82 icocz pu-1 1 float 1 3 vcc_tsi f15 d19 tsi_xm tsi_xm iaoa hi-z hi-z hi-z a16 e18 tsi_xp tsi_xp iaoa hi-z hi-z hi-z table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 79 c14 d18 tsi_ym tsi_ym iaoa hi-z hi-z hi-z / 0 8 b17 e17 tsi_yp tsi_yp iaoa hi-z hi-z hi-z vcc_usb e5 a5 usbh1_n usbh1_n iaoa pd-0 note[ 8 ]pd-0 8 pd-0 8 e6 a6 usbh1_p usbh1_p iaoa pd-0 note[ 8 ]pd-0 8 pd-0 8 d5 a3 usbotg_n usbotg_n iaoa hi-z hi-z or pd-0 9 hi-z or pd-0 9 c5 a4 usbotg_p usbotg_p iaoa hi-z hi-z or pd-0 or pu-1 8 , 10 hi-z or pd-0 or pu-1 8 , 10 vcc_card1 w15 ae20 gpio18 gpio18 icocz pd-0 1 float 1 3 w16 ab20 gpio19 gpio19 icocz pd-0 1 float 1 3 u15 ac21 gpio20 gpio20 icocz pd-0 1 float 1 3 aa16 af22 gpio21 gpio21 icocz pu-1 1 float 1 3 v17 ac22 gpio22 gpio22 icocz pd-0 1 float 1 3 y17 af23 gpio23 gpio23 icocz pd-0 1 float 1 3 vcc_card2 w19 ae22 gpio24 gpio24 icocz pd-0 1 float 1 3 w18 ad22 gpio25 gpio25 icocz pd-0 1 float 1 3 aa19 af24 gpio26 gpio26 icocz pd-0 1 float 1 3 v16 ad23 gpio27 gpio27 icocz pu-1 1 float 1 3 u19 ab22 gpio28 gpio28 icocz pd-0 1 float 1 3 u16 ae25 gpio29 gpio29 icocz pd-0 1 float 1 3 no connect balls a1 a1 nc a2 a2 nc a20 a25 nc a21 a26 nc table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 80 april 6, 2009 released aa1 b1 nc aa2 b26 nc aa20 ae1 nc aa21 ae2 nc b1 ae26 nc b21 af1 nc y1 af2 nc y21 af25 nc y7 af26 nc reserved for future use (rfu) balls a4 k3 rfu_a4/ rfu_k3 b10 r2 rfu_b10/ rfu_r2 b11 t1 rfu_b11/ rfu_t1 b3 t2 rfu_b3/ rfu_t2 c3 t3 rfu_c3/ rfu_t3 d4 u1 rfu_d4/ rfu_u1 d6 u2 rfu_d6/ rfu_u2 h7 u3 rfu_h7/ rfu_u3 l7 u4 rfu_l7/ rfu_u4 y19 ad4 rfu_y19/ rfu_ad4 y20 rfu_y20 package on package (pop) signals table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 81 d13 lock_pre input input input w20 nd_rst input input input c20 df_nwp input input input power supplies l5 ac14 vcc_apps vcc_apps ps input input input m5 ac16 vcc_apps vcc_apps ps input input input p5 ac20 vcc_apps vcc_apps ps input input input l6 ad19 vcc_apps vcc_apps ps input input input n6 ae16 vcc_apps vcc_apps ps input input input n7 af15 vcc_apps vcc_apps ps input input input e8 af18 vcc_apps vcc_apps ps input input input v12 af20 vcc_apps vcc_apps ps input input input w13 af21 vcc_apps vcc_apps ps input input input n14 l13 vcc_apps vcc_apps ps input input input aa14 l14 vcc_apps vcc_apps ps input input input v15 m13 vcc_apps vcc_apps ps input input input y15 m14 vcc_apps vcc_apps ps input input input aa15 n11 vcc_apps vcc_apps ps input input input y16 n12 vcc_apps vcc_apps ps input input input n15 vcc_apps vcc_apps ps input input input n16 vcc_apps vcc_apps ps input input input p11 vcc_apps vcc_apps ps input input input p12 vcc_apps vcc_apps ps input input input p15 vcc_apps vcc_apps ps input input input p16 vcc_apps vcc_apps ps input input input r13 vcc_apps vcc_apps ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 82 april 6, 2009 released r14 vcc_apps vcc_apps ps input input input t13 vcc_apps vcc_apps ps input input input t14 vcc_apps vcc_apps ps input input input t25 vcc_apps vcc_apps ps input input input v25 vcc_apps vcc_apps ps input input input h9 a10 vcc_bbatt vcc_bbatt ps input input input g10 d9 vcc_bg vcc_bg ps input input input aa17 ab21 vcc_card1 vcc_card1 ps input input input w17 ae23 vcc_card2 vcc_card2 ps input input input m15 r26 vcc_ci vcc_ci ps input input input v24 vcc_ci vcc_ci ps input input input b4 ab7 vcc_df vcc_df ps input input input t5 ac9 vcc_df vcc_df ps input input input v6 ad6 vcc_df vcc_df ps input input input b9 ae11 vcc_df vcc_df ps input input input ae13 vcc_df vcc_df ps input input input b15 d15 vcc_io1 vcc_io1 ps input input input e10 vcc_io1 vcc_io1 ps input input input aa13 ab18 vcc_io3 vcc_io3 ps input input input u18 ab24 vcc_io4 vcc_io4 ps input input input w23 vcc_io4 vcc_io4 ps input input input e15 b22 vcc_io6 vcc_io6 ps input input input c20 vcc_io6 vcc_io6 ps input input input k18 j26 vcc_lcd vcc_lcd ps input input input k20 n24 vcc_lcd vcc_lcd ps input input input b2 ab5 vcc_mem vcc_mem ps input input input n2 d4 vcc_mem vcc_mem ps input input input p2 f4 vcc_mem vcc_mem ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 83 d3 h4 vcc_mem vcc_mem ps input input input l3 j5 vcc_mem vcc_mem ps input input input m3 k5 vcc_mem vcc_mem ps input input input aa3 m5 vcc_mem vcc_mem ps input input input n4 p5 vcc_mem vcc_mem ps input input input k5 t5 vcc_mem vcc_mem ps input input input m7 w5 vcc_mem vcc_mem ps input input input y5 vcc_mem vcc_mem ps input input input g19 f24 vcc_msl vcc_msl ps input input input f3 ab26 vcc_mvt vcc_mvt ps input input input p3 ab8 vcc_mvt vcc_mvt ps input input input f4 ad15 vcc_mvt vcc_mvt ps input input input p4 e20 vcc_mvt vcc_mvt ps input input input l8 e7 vcc_mvt vcc_mvt ps input input input n15 g23 vcc_mvt vcc_mvt ps input input input e17 h5 vcc_mvt vcc_mvt ps input input input m4 vcc_mvt vcc_mvt ps input input input p22 vcc_mvt vcc_mvt ps input input input w4 vcc_mvt vcc_mvt ps input input input f10 e8 vcc_osc13m vcc_osc13m ps input input input f12 ae18 vcc_pll vcc_pll ps input input input r12 b15 vcc_pll vcc_pll ps input input input g1 ab11 vcc_sram vcc_sram ps input input input g2 d16 vcc_sram vcc_sram ps input input input p9 e9 vcc_sram vcc_sram ps input input input f14 h26 vcc_sram vcc_sram ps input input input a19 j3 vcc_sram vcc_sram ps input input input e12 a18 vcc_tsi vcc_tsi ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 84 april 6, 2009 released b6 c5 vcc_usb vcc_usb ps input input input d1 aa26 vss vss ps input input input u1 ab12 vss vss ps input input input v1 ab9 vss vss ps input input input v2 ad14 vss vss ps input input input n3 ad16 vss vss ps input input input c4 ad17 vss vss ps input input input m4 ad18 vss vss ps input input input j5 ad21 vss vss ps input input input v7 ae15 vss vss ps input input input f8 ae19 vss vss ps input input input u11 ae21 vss vss ps input input input w11 g25 vss vss ps input input input e14 g26 vss vss ps input input input v14 l11 vss vss ps input input input p17 l12 vss vss ps input input input y18 l15 vss vss ps input input input aa18 l16 vss vss ps input input input p21 m11 vss vss ps input input input m12 vss vss ps input input input m15 vss vss ps input input input m16 vss vss ps input input input n13 vss vss ps input input input n14 vss vss ps input input input n22 vss vss ps input input input p13 vss vss ps input input input p14 vss vss ps input input input r11 vss vss ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 85 r12 vss vss ps input input input r15 vss vss ps input input input r16 vss vss ps input input input t11 vss vss ps input input input t12 vss vss ps input input input t15 vss vss ps input input input t16 vss vss ps input input input t26 vss vss ps input input input v26 vss vss ps input input input y4 vss vss ps input input input a9 vss vss ps input input input c8 b9 vss_bbatt vss_bbatt ps input input input c9 d10 vss_bg vss_bg ps input input input r14 ad20 vss_card1 vss_card1 ps input input input v19 ae24 vss_card2 vss_card2 ps input input input n16 r25 vss_ci vss_ci ps input input input u24 vss_ci vss_ci ps input input input a3 ac10 vss_df vss_df ps input input input w6 ac6 vss_df vss_df ps input input input y10 ac7 vss_df vss_df ps input input input y12 ad13 vss_df vss_df ps input input input b20 af11 vss_df vss_df ps input input input d11 e11 vss_io1 vss_io1 ps input input input e15 vss_io1 vss_io1 ps input input input t12 ae17 vss_io3 vss_io3 ps input input input r17 ab23 vss_io4 vss_io4 ps input input input y24 vss_io4 vss_io4 ps input input input e19 c22 vss_io6 vss_io6 ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 86 april 6, 2009 released d20 vss_io6 vss_io6 ps input input input r11 j25 vss_lcd vss_lcd ps input input input j21 m23 vss_lcd vss_lcd ps input input input c1 aa5 vss_mem vss_mem ps input input input h1 ac5 vss_mem vss_mem ps input input input m1 e4 vss_mem vss_mem ps input input input p1 g4 vss_mem vss_mem ps input input input r1 j4 vss_mem vss_mem ps input input input t1 l5 vss_mem vss_mem ps input input input k2 n5 vss_mem vss_mem ps input input input r4 r5 vss_mem vss_mem ps input input input r5 u5 vss_mem vss_mem ps input input input p7 v5 vss_mem vss_mem ps input input input w21 vss_mem vss_mem ps input input input g17 f26 vss_msl vss_msl ps input input input a9 b11 vss_osc13m vss_osc13m ps input input input c12 ac18 vss_pll vss_pll ps input input input w14 c14 vss_pll vss_pll ps input input input d14 c18 vss_tsi vss_tsi ps input input input e3 b5 vss_usb vss_usb ps input input input table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 87 4.2.2 pxa31x processor pin use table 10 lists the mapping of signals to specific pxa31x processor package pins. note: 1. gpio reset/s3 operation: after any reset is asserted or if pxa32x processor is in s3/d4/c4 power mode, these pins are configured as the primary function of the mfp (generally as gpio input) and default pullup or pulldown occurs. 2. crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators and are not affected by either reset or s2/d3/c4 power mode. for more information, se e the ?services clock control unit? chapter in the pxa3xx processor family developers manual . 3. each mfp output value is based on mfprxx[sleep_sel], mfprxx[sleep_data], mfprxx[sleep_oe_n], mfprxx[pull_sel], mfprxx[pullup_en] and mfprxx[pulldown_en] following s2/d3/c4 wake-up. to prevent unnecessary current drain, ensure input signals are not floating during low-power modes. each gpio to be driven can be programmed to a 0/1 or be pulled up or pulled down during s2/d3/c4 power mode if the mvt and the io (hvt) supplies are present. 4. logic low when oscc[tensx] bit is cleared, clk_tout when oscc[tensx] is set. configure tens2 for s2/d3/c4 mode and tens3 for s3/d4/c4 power mode. 5. pulldown always enabled. 6. output functions during s2/d3/c4 power mode. 7. pullup always enabled. 8. ad2d0er[wetsi] bit is set before entry into s2, tsi_ym is driven low (not pulled low). ad2d0er[wetsi] bit is clear before entry into s2, tsi_ym signal is hi-z (no pulldown or pullup). 9. 20 k nominal, 14.5 k min - 24.5 k max 10. pd-0 if up2ocr[dmpde] is set, then pd-0, hi-z if up2ocr[dmpde] is cleared. 11. hi-z if up2ocr[dppde] is cleared and up2ocr[dppue] is cleared; pu-1 if up2ocr[dppde] is cleared and up2ocr[dppue] is set; pd-0 if up2ocr[dppde] is set and up2ocr[dppue] is cleared. setting up2ocr[dppde] and up2ocr[dppue] at the same time is not allowed. 12. this signal?s pullup/pulldown is enabled during power-on, hardware, global watchdog and gpio resets. the pullup/pulldown must be disabled by software by setting pcfr[pudh] after the external devices driving these pins are configured. 13. there is no pullup or pulldown on this pin. asserts if pcfr[sl_rod] is clear. 14. see tab le 1 2 for type definitions table 9: pxa32x processor pin usage summary (continued) 15mm 2 ball # 14mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode table 10: pxa31x processor pin usage summary 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode vcc_bbatt b6 a6 clk_tout clk_tout oc clk-out 44 b7 e6 ext_wakeup 0 ext_wakeup0 icocz pd-0 10 pd-0 10 pd-0 10 c6 c6 nbatt_fault nbatt_fault ic input input input e8 e9 ngpio_rese t ngpio_reset ic pu-1 10 pu-1 10 pu-1 10 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 88 april 6, 2009 released d6 b6 nreset nreset ic input 7 input input f9 a8 nreset_out nreset_out oc low 11 11 a6 e5 ntrst ntrst ic input 7 input 7 input 7 a7 a7 pwr_cap0 pwr_cap0 oa - - - f8 f7 pwr_cap1 pwr_cap1 oa - - - d3 c5 pwr_en pwr_en oc low low low c7 b7 pwr_out pwr_out oa - - - d4 f6 sys_en sys_en oc low low low c4 a5 tck tck ic input input input e3 b5 tdi tdi ic input 7 input 7 input 7 d2 c4 tdo tdo ocz hi-z hi-z hi-z c3 d3 tms tms ic input 7 input 7 input 7 a8 c7 txtal_in txtal_in ia 222 b8 c8 txtal_out txtal_out oa 222 vcc_mvt b9 a9 pxtal_in pxtal_in ia 222 c9 b9 pxtal_out pxtal_out oa 222 vcc_io1 a11 a13 gpio0_2 gpio0_2 icocz pd-0 1 float 1 3 d11 a12 gpio1_2 gpio1_2 icocz pd-0 1 float 1 3 e18 d22 gpio91 gpio91 icocz pu-1 1 float 1 3 e21 c22 gpio92 gpio92 icocz pu-1 1 float 1 3 e20 e24 gpio93 gpio93 icocz pd-0 1 float 1 3 d21 c23 gpio94 gpio94 icocz pd-0 1 float 1 3 c20 d24 gpio95 gpio95 icocz pd-0 1 float 1 3 a19 b23 gpio96 gpio96 icocz pd-0 1 float 1 3 d20 a22 gpio97 gpio97 icocz pd-0 1 float 1 3 c21 c24 gpio98 gpio98 icocz pd-0 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 89 a18 b16 gpio99 gpio99 icocz pd-0 1 float 1 3 b18 a21 gpio100 gpio100 icocz pd-0 1 float 1 3 c19 b19 gpio101 gpio101 icocz pu-1 1 float 1 3 a17 a20 gpio102 gpio102 icocz pu-1 1 float 1 3 d18 c20 gpio103 gpio103 icocz pu-1 1 float 1 3 e19 c19 gpio104 gpio104 icocz pu-1 1 float 1 3 d17 f17 gpio105 gpio105 icocz pu-1 1 float 1 3 b17 b20 gpio106 gpio106 icocz pu-1 1 float 1 3 c16 a17 gpio107 gpio107 icocz pu-1 1 float 1 3 c17 c18 gpio108 gpio108 icocz pu-1 1 float 1 3 d16 f16 gpio109 gpio109 icocz pd-0 1 float 1 3 a16 a19 gpio110 gpio110 icocz pu-1 1 float 1 3 f14 e15 gpio111 gpio111 icocz pu-1 1 float 1 3 b15 h16 gpio112 gpio112 icocz pd-0 1 float 1 3 c15 b15 gpio113 gpio113 icocz pd-0 1 float 1 3 d15 e16 gpio114 gpio114 icocz pu-1 1 float 1 3 c13 a15 gpio115 gpio115 icocz pd-0 1 float 1 3 a14 a16 gpio116 gpio116 icocz pd-0 1 float 1 3 e14 e14 gpio117 gpio117 icocz pd-0 1 float 1 3 d14 c15 gpio118 gpio118 icocz pd-0 1 float 1 3 e13 b14 gpio119 gpio119 icocz pd-0 1 float 1 3 b14 f15 gpio120 gpio120 icocz pd-0 1 float 1 3 f13 e13 gpio121 gpio121 icocz pd-0 1 float 1 3 c14 f14 gpio122 gpio122 icocz pd-0 1 float 1 3 d13 b13 gpio123 gpio123 icocz pu-1 1 float 1 3 b12 f13 gpio124 gpio124 icocz pd-0 1 float 1 3 f12 f12 gpio125 gpio125 icocz pd-0 1 float 1 3 a12 a14 gpio126 gpio126 icocz pu-1 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 90 april 6, 2009 released c12 c12 gpio127 gpio127 icocz pu-1 1 float 1 3 p8 e20 gpio7_2 gpio7_2 icocz pd-0 1 float 1 3 n8 f19 gpio8_2 gpio8_2 icocz pd-0 1 float 1 3 k8 e18 gpio9_2 gpio9_2 icocz pd-0 1 float 1 3 j8 f18 gpio10_2 gpio10_2 icocz pd-0 1 float 1 3 f10 a10 pwr_scl pwr_scl icocz pu-1 10 pu-1 10 float - note[ 1 ] b10 f11 pwr_sda pwr_sda icocz pu-1 10 pu-1 10 float - note[ 1 ] b11 h12 test test ic input 5 input 5 input 5 f11 e10 testclk testclk ic input 5 input 5 input 5 e10 b10 vctcxo_en vctcxo_en oc low note 6 note 6 c11 b12 clk_pout clk_pout oc low float low vcc_df aa4 ac4 df_addr0 df_addr0 ocz pd-0 1 float 1 3 v6 ab5 df_addr1 df_addr1 ocz pd-0 1 float 1 3 w6 ad4 df_addr2 df_addr2 ocz pd-0 1 float 1 3 y4 ac5 df_addr3 df_addr3 ocz pd-0 1 float 1 3 aa5 y7 df_io0 df_io0 icocz pd-0 1 float 1 3 aa6 ac7 df_io1 df_io1 icocz pd-0 1 float 1 3 w7 ad6 df_io2 df_io2 icocz pd-0 1 float 1 3 y8 ab9 df_io3 df_io3 icocz pd-0 1 float 1 3 v10 ad12 df_io4 df_io4 icocz pd-0 1 float 1 3 w13 ad13 df_io5 df_io5 icocz pd-0 1 float 1 3 w12 ad14 df_io6 df_io6 icocz pd-0 1 float 1 3 v11 y12 df_io7 df_io7 icocz pd-0 1 float 1 3 u8 ad5 df_io8 df_io8 icocz pd-0 1 float 1 3 y5 ab8 df_io9 df_io9 icocz pd-0 1 float 1 3 y6 ad7 df_io10 df_io10 icocz pd-0 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 91 w8 ad9 df_io11 df_io11 icocz pd-0 1 float 1 3 u15 w13 df_io12 df_io12 icocz pd-0 1 float 1 3 w10 ab12 df_io13 df_io13 icocz pd-0 1 float 1 3 w11 y14 df_io14 df_io14 icocz pd-0 1 float 1 3 w15 ad15 df_io15 df_io15 icocz pd-0 1 float 1 3 v7 ac2 df_ale_nwe df_ale ocz pu-1 1 float 1 3 v9 w10 df_ncs0 df_ncs0 ocz pu-1 1 float 1 3 u10 ac13 df_ncs1 df_ncs1 ocz pu-1 1 float 1 3 w5 ab3 df_nre df_noe ocz pu-1 1 float 1 3 w4 ab2 df_nwe df_nwe ocz pu-1 1 float 1 3 w3 aa3 df_int_rnb df_rnb icz pu-1 1 float 1 3 v8 w6 df_cle_noe nd_cle ocz pu-1 1 float 1 3 aa10 ac11 df_sclk_e df_sclk_e ocz pd-0 1 float 1 3 v3 w1 gpio0 gpio0 icocz pd-0 1 float 1 3 u4 aa2 gpio1 gpio1 icocz pu-1 1 float 1 3 v1 y1 gpio2 gpio2 icocz pu-1 1 float 1 3 y3 ad3 nbe0 nbe0 ocz pu-1 1 float 1 3 aa3 ac3 nbe1 nbe1 ocz pu-1 1 float 1 3 y10 ab11 nlla nlla ocz pu-1 1 float 1 3 y9 ad10 nlua nlua ocz pu-1 1 float 1 3 w1 ab1 ncs0 ncs0 oc high high high v4 aa1 ncs1 ncs1 oc high high high vcc_io3 w17 ac21 gpio17 gpio17 icocz pd-0 1 float 1 3 w18 w17 gpio18 gpio18 icocz pd-0 1 float 1 3 u17 ab21 gpio19 gpio19 icocz pd-0 1 float 1 3 v18 ab23 gpio20 gpio20 icocz pu-1 1 float 1 3 w19 y22 gpio21 gpio21 icocz pu-1 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 92 april 6, 2009 released aa17 ac23 gpio22 gpio22 icocz pu-1 1 float 1 3 y17 ab22 gpio23 gpio23 icocz pu-1 1 float 1 3 aa18 ad22 gpio24 gpio24 icocz pd-0 1 float 1 3 y18 aa23 gpio25 gpio25 icocz pd-0 1 float 1 3 y19 aa24 gpio26 gpio26 icocz pd-0 1 float 1 3 v21 w19 gpio27 gpio27 icocz pd-0 1 float 1 3 u21 y23 gpio28 gpio28 icocz pd-0 1 float 1 3 v19 y24 gpio29 gpio29 icocz pd-0 1 float 1 3 e6 w15 gpio2_2 gpio2_2 icocz pu-1 1 float 1 3 e5 w20 gpio3_2 gpio3_2 icocz pd-0 1 float 1 3 g8 y18 gpio4_2 gpio4_2 icocz pd-0 1 float 1 3 f5 y20 gpio5_2 gpio5_2 icocz pd-0 1 float 1 3 e7 y19 gpio6_2 gpio6_2 icocz pu-1 1 float 1 3 vcc_ulpi v20 aa22 gpio30 gpio30 icocz pd-0 1 float 1 3 u18 w22 gpio31 gpio31 icocz pd-0 1 float 1 3 u20 w23 gpio32 gpio32 icocz pu-1 1 float 1 3 u19 w18 gpio33 gpio33 icocz pu-1 1 float 1 3 t20 w24 gpio34 gpio34 icocz pu-1 1 float 1 3 t18 v20 gpio35 gpio35 icocz pu-1 1 float 1 3 t21 v23 gpio36 gpio36 icocz pu-1 1 float 1 3 r17 v19 gpio37 gpio37 icocz pu-1 1 float 1 3 t17 u22 gpio38 gpio38 icocz pd-0 1 float 1 3 v17 n17 ulpi_dir ulpi_dir ic pd-0 1 float 1 3 w20 p17 ulpi_nxt ulpi_nxt ic pd-0 1 float 1 3 w21 u17 ulpi_stp ulpi_stp 0c pu-1 1 float 1 3 vcc_ci r18 u19 gpio39 gpio39 icocz pd-0 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 93 t19 v24 gpio40 gpio40 icocz pd-0 1 float 1 3 r20 u23 gpio41 gpio41 icocz pd-0 1 float 1 3 r19 t22 gpio42 gpio42 icocz pd-0 1 float 1 3 p16 u24 gpio43 gpio43 icocz pd-0 1 float 1 3 r21 t20 gpio44 gpio44 icocz pd-0 1 float 1 3 p17 r20 gpio45 gpio45 icocz pd-0 1 float 1 3 p18 t17 gpio46 cif_dd7 icocz pd-0 1 float 1 3 n16 p22 gpio47 gpio47 icocz pd-0 1 float 1 3 p21 r19 gpio48 gpio48 icocz pd-0 1 float 1 3 n17 p20 gpio49 cif_mclk icocz pd-0 1 float 1 3 n18 r24 gpio50 cif_pclk icocz pd-0 1 float 1 3 n19 n24 gpio51 cif_hsync icocz pd-0 1 float 1 3 m20 n20 gpio52 cif_vsync icocz pd-0 1 float 1 3 vcc_lcd m17 r23 gpio53 gpio53 icocz pu-1 1 float 1 3 m21 p23 gpio54 gpio54 icocz pd-0 1 float 1 3 m18 n22 gpio55 gpio55 icocz pd-0 1 float 1 3 l18 p24 gpio56 gpio56 icocz pd-0 1 float 1 3 m19 n23 gpio57 gpio57 icocz pd-0 1 float 1 3 l20 p19 gpio58 gpio58 icocz pd-0 1 float 1 3 l17 m19 gpio59 gpio59 icocz pd-0 1 float 1 3 l21 l19 gpio60 gpio60 icz pd-0 1 float 1 3 k19 m22 gpio61 gpio61 icocz pd-0 1 float 1 3 l19 m23 gpio62 gpio62 icocz pu-1 1 float 1 3 k20 j19 gpio63 gpio63 icocz pd-0 1 float 1 3 k17 m24 gpio64 gpio64 icocz pd-0 1 float 1 3 j17 l22 gpio65 gpio65 icocz pd-0 1 float 1 3 k21 k22 gpio66 gpio66 icocz pd-0 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 94 april 6, 2009 released j18 l23 gpio67 gpio67 icocz pd-0 1 float 1 3 k18 l20 gpio68 gpio68 icocz pd-0 1 float 1 3 j19 k20 gpio69 gpio69 icocz pd-0 1 float 1 3 j20 l24 gpio70 gpio70 icocz pd-0 1 float 1 3 j16 h19 gpio71 gpio71 icocz pd-0 1 float 1 3 j21 k23 gpio72 gpio72 icocz pd-0 1 float 1 3 h16 k24 gpio73 gpio73 icocz pd-0 1 float 1 3 h17 j22 gpio74 gpio74 icocz pd-0 1 float 1 3 h18 g19 gpio75 gpio75 icocz pd-0 1 float 1 3 h20 j23 gpio76 gpio76 icocz pd-0 1 float 1 3 vcc_mem g3 f2 dqm0 dqm0 oc high high high t4 u1 dqm1 dqm1 oc high high high f3 g3 dqs0 dqs0 isocz pd-0 pd-0 pd-0 r4 v3 dqs1 dqs1 isocz pd-0 pd-0 pd-0 l3 m1 ma0 ma0 oc high high high n4 r5 ma1 ma1 oc high high high h3 h2 ma2 ma2 oc high high high m1 p5 ma3 ma3 oc high high high h4 k3 ma4 ma4 oc high high high m3 p3 ma5 ma5 oc high high high k4 j1 ma6 ma6 oc high high high m2 n3 ma7 ma7 oc high high high j1 k2 ma8 ma8 oc high high high l2 n1 ma9 ma9 oc high high high j3 k1 sdma10 sdma10 oc high high high m4 n2 ma11 ma11 oc high high high k3 l3 ma12 ma12 oc high high high table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 95 h5 m5 ma13 ma13 oc high high high h2 j3 ma14 ma14 oc high high high j4 j2 ma15 ma15 oc high high high d1 d1 md0 md0 icsocz pd-0 pd-0 pd-0 e1 e1 md1 md1 icsocz pd-0 pd-0 pd-0 e2 e2 md2 md2 icsocz pd-0 pd-0 pd-0 f1 f1 md3 md3 icsocz pd-0 pd-0 pd-0 f2 g1 md4 md4 icsocz pd-0 pd-0 pd-0 g1 g2 md5 md5 icsocz pd-0 pd-0 pd-0 g2 h3 md6 md6 icsocz pd-0 pd-0 pd-0 h1 h1 md7 md7 icsocz pd-0 pd-0 pd-0 p3 t2 md8 md8 icsocz pd-0 pd-0 pd-0 r3 t1 md9 md9 icsocz pd-0 pd-0 pd-0 r1 u3 md10 md10 icsocz pd-0 pd-0 pd-0 t2 u2 md11 md11 icsocz pd-0 pd-0 pd-0 t1 v2 md12 md12 icsocz pd-0 pd-0 pd-0 u2 v1 md13 md13 icsocz pd-0 pd-0 pd-0 t3 w2 md14 md14 icsocz pd-0 pd-0 pd-0 u1 w3 md15 md15 icsocz pd-0 pd-0 pd-0 n3 t3 nsdcas nsdcas oc high high high l1 m3 nsdcs0 nsdcs0 oc high high high j2 m2 nsdcs1 nsdcs1 oc high high high p2 p2 nsdras nsdras oc high high high p1 r3 nsdwe nsdwe oc high high high n1 p1 rcomp_ddr rcomp_ddr oa - - - r2 r2 sdcke sdcke oc low low low k1 l1 sdclk0 sdclk0 oc low low low k2 l2 sdclk1 sdclk1 oc high high high table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 96 april 6, 2009 released vcc_msl h19 h22 gpio77 gpio77 icocz pd-0 1 float 1 3 g16 j24 gpio78 gpio78 icocz pd-0 1 float 1 3 f16 j20 gpio79 gpio79 icocz pd-0 1 float 1 3 h21 h23 gpio80 gpio80 icocz pd-0 1 float 1 3 g18 g23 gpio81 gpio81 icocz pd-0 1 float 1 3 g20 g22 gpio82 gpio82 icocz pd-0 1 float 1 3 g19 f23 gpio83 gpio83 icocz pd-0 1 float 1 3 g21 f20 gpio84 gpio84 icocz pu-1 1 float 1 3 f19 f22 gpio85 gpio85 icocz pd-0 1 float 1 3 e16 h24 gpio86 gpio86 icocz pd-0 1 float 1 3 f18 e23 gpio87 gpio87 icocz pd-0 1 float 1 3 f20 e22 gpio88 gpio88 icocz pd-0 1 float 1 3 e17 g24 gpio89 gpio89 icocz pu-1 1 float 1 3 f21 d23 gpio90 gpio90 icocz pu-1 1 float 1 3 vcc_card1 u11 ab14 gpio3 gpio3 icocz pd-0 1 float 1 3 aa11 ac14 gpio4 gpio4 icocz pd-0 1 float 1 3 v12 ab15 gpio5 gpio5 icocz pd-0 1 float 1 3 v13 ad17 gpio6 gpio6 icocz pu-1 1 float 1 3 w14 ab17 gpio7 gpio7 icocz pd-0 1 float 1 3 u14 y16 gpio8 gpio8 icocz pd-0 1 float 1 3 vcc_card2 u12 ad16 gpio9 gpio9 icocz pd-0 1 float 1 3 y14 ab18 gpio10 gpio10 icocz pd-0 1 float 1 3 v14 ab19 gpio11 gpio11 icocz pd-0 1 float 1 3 u16 ac20 gpio12 gpio12 icocz pu-1 1 float 1 3 v15 ac19 gpio13 gpio13 icocz pd-0 1 float 1 3 table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 97 y15 ad20 gpio14 gpio14 icocz pd-0 1 float 1 3 y16 y17 gpio15 gpio15 icocz pu-1 1 float 1 3 v16 ad19 gpio16 gpio16 icocz pu-1 1 float 1 3 rfu balls a3 a3 rfu_a3/rfu_ a3 ????? a4 b2 rfu_a4/rfu_ b2 ????? a5 b3 rfu_a5/rfu_ b3 ????? b5 b4 rfu_b5/rfu_ b4 ????? n2 c3 rfu_n2/rfu_ c3 ????? w9 r1 rfu_w9/rfu_ r1 ????? ad11 rfu_ad11 ? ? ? ? ? no connect (nc) balls b4 a1 nc ? ? ? ? ? c1 a2 nc ? ? ? ? ? c5 a23 nc ? ? ? ? ? d19 a24 nc ? ? ? ? ? g4 b1 nc ? ? ? ? ? l4 b24 nc ? ? ? ? ? l8 e17 nc ? ? ? ? ? m8 e19 nc ? ? ? ? ? p4 w5 nc ? ? ? ? ? p5 w7 nc ? ? ? ? ? u3 w8 nc ? ? ? ? ? u13 w9 nc ? ? ? ? ? v2 w12 nc ? ? ? ? ? table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 98 april 6, 2009 released w2 y9 nc ? ? ? ? ? aa19 ab6 nc ? ? ? ? ? ac1 nc ? ? ? ? ? ac6 nc ? ? ? ? ? ac24 nc ? ? ? ? ? ad1 nc ? ? ? ? ? ad2 nc ? ? ? ? ? ad23 nc ? ? ? ? ? ad24 nc ? ? ? ? ? internal nand signals u5 df_nwp df_nwp input input input input power supplies a10 b17 vcc_apps vcc_apps ps input input input a13 c14 vcc_apps vcc_apps ps input input input a15 e11 vcc_apps vcc_apps ps input input input h10 h10 vcc_apps vcc_apps ps input input input h11 h15 vcc_apps vcc_apps ps input input input h12 k8 vcc_apps vcc_apps ps input input input k14 k17 vcc_apps vcc_apps ps input input input l5 l5 vcc_apps vcc_apps ps input input input l14 r8 vcc_apps vcc_apps ps input input input m14 r17 vcc_apps vcc_apps ps input input input n5 t24 vcc_apps vcc_apps ps input input input n21 u10 vcc_apps vcc_apps ps input input input p10 u15 vcc_apps vcc_apps ps input input input p11 ab16 vcc_apps vcc_apps ps input input input p12 ac9 vcc_apps vcc_apps ps input input input y13 vcc_apps vcc_apps ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 99 aa7 vcc_apps vcc_apps ps input input input aa9 vcc_apps vcc_apps ps input input input aa12 vcc_apps vcc_apps ps input input input c8 e8 vcc_bbatt vcc_bbatt ps input input input d10 c9 vcc_bg vcc_bg ps input input input y11 ac15 vcc_card1 vcc_card1 ps input input input aa14 ad18 vcc_card2 vcc_card2 ps input input input p15 r22 vcc_ci vcc_ci ps input input input p20 vcc_ci vcc_ci ps input input input g11 y6 vcc_df vcc_df ps input input input t9 ab4 vcc_df vcc_df ps input input input t10 ab7 vcc_df vcc_df ps input input input t11 ab10 vcc_df vcc_df ps input input input t12 ab13 vcc_df vcc_df ps input input input t13 ac12 vcc_df vcc_df ps input input input e15 a11 vcc_io1 vcc_io1 ps input input input g10 c16 vcc_io1 vcc_io1 ps input input input g15 f24 vcc_io1 vcc_io1 ps input input input t16 ab20 vcc_io3 vcc_io3 ps input input input k16 k19 vcc_lcd vcc_lcd ps input input input l16 vcc_lcd vcc_lcd ps input input input m16 vcc_lcd vcc_lcd ps input input input d5 d2 vcc_mem vcc_mem ps input input input g5 e3 vcc_mem vcc_mem ps input input input g6 f3 vcc_mem vcc_mem ps input input input h6 g5 vcc_mem vcc_mem ps input input input j6 j5 vcc_mem vcc_mem ps input input input k6 k5 vcc_mem vcc_mem ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 100 april 6, 2009 released l6 n5 vcc_mem vcc_mem ps input input input m6 t5 vcc_mem vcc_mem ps input input input n6 v5 vcc_mem vcc_mem ps input input input p6 y2 vcc_mem vcc_mem ps input input input r6 vcc_mem vcc_mem ps input input input t6 vcc_mem vcc_mem ps input input input u6 vcc_mem vcc_mem ps input input input v5 vcc_mem vcc_mem ps input input input g17 h20 vcc_msl vcc_msl ps input input input e4 b18 vcc_mvt vcc_mvt ps input input input g9 c21 vcc_mvt vcc_mvt ps input input input g14 f9 vcc_mvt vcc_mvt ps input input input h15 h6 vcc_mvt vcc_mvt ps input input input j5 n19 vcc_mvt vcc_mvt ps input input input j15 p6 vcc_mvt vcc_mvt ps input input input n15 u6 vcc_mvt vcc_mvt ps input input input r14 w16 vcc_mvt vcc_mvt ps input input input t5 ac8 vcc_mvt vcc_mvt ps input input input u9 vcc_mvt vcc_mvt ps input input input d9 b8 vcc_osc13m vcc_osc13m ps input input input d12 c11 vcc_pll vcc_pll ps input input input aa16 ac22 vcc_pll vcc_pll ps input input input b19 b21 vcc_sram vcc_sram ps input input input c18 w11 vcc_sram vcc_sram ps input input input aa8 vcc_sram vcc_sram ps input input input b3 a4 vcc_bias vcc_bias ps input input input r16 v22 vcc_ulpi vcc_ulpi ps input input input a1 vss vss ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 101 a2 vss vss ps input input input b1 vss vss ps input input input b2 vss vss ps input input input c17 vss vss ps input input input e7 vss vss ps input input input a9 e12 vss vss ps input input input a20 h8 vss vss ps input input input a21 h9 vss vss ps input input input h11 vss vss ps input input input h13 vss vss ps input input input b13 h14 vss vss ps input input input b16 h17 vss vss ps input input input b20 j8 vss vss ps input input input b21 j17 vss vss ps input input input c2 l8 vss vss ps input input input f4 l17 vss vss ps input input input h8 m6 vss vss ps input input input h9 m8 vss vss ps input input input h13 m17 vss vss ps input input input h14 n8 vss vss ps input input input j14 p8 vss vss ps input input input k5 t8 vss vss ps input input input m5 t23 vss vss ps input input input n14 u5 vss vss ps input input input n20 u8 vss vss ps input input input p9 u9 vss vss ps input input input p13 u11 vss vss ps input input input p14 u12 vss vss ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 102 april 6, 2009 released r5 u13 vss vss ps input input input r8 u14 vss vss ps input input input t8 u16 vss vss ps input input input t14 ac10 vss vss ps input input input y7 ac16 vss vss ps input input input aa13 ac17 vss vss ps input input input d7 ad8 vss vss ps input input input d8 f8 vss_bbatt vss_bbatt ps input input input c10 f10 vss_bg vss_bg ps input input input y12 y15 vss_card1 vss_card1 ps input input input aa15 ac18 vss_card2 vss_card2 ps input input input p19 t19 vss_ci vss_ci ps input input input g12 w14 vss_df vss_df ps input input input r9 y5 vss_df vss_df ps input input input r10 y8 vss_df vss_df ps input input input r11 y10 vss_df vss_df ps input input input r12 y11 vss_df vss_df ps input input input r13 y13 vss_df vss_df ps input input input y1 vss_df vss_df ps input input input y2 vss_df vss_df ps input input input aa1 vss_df vss_df ps input input input aa2 vss_df vss_df ps input input input f15 a18 vss_io1 vss_io1 ps input input input g13 b11 vss_io1 vss_io1 ps input input input b22 vss_io1 vss_io1 ps input input input t15 ab24 vss_io3 vss_io3 ps input input input y20 vss_io3 vss_io3 ps input input input y21 vss_io3 vss_io3 ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 103 aa20 vss_io3 vss_io3 ps input input input aa21 vss_io3 vss_io3 ps input input input k15 m20 vss_lcd vss_lcd ps input input input l15 vss_lcd vss_lcd ps input input input m15 vss_lcd vss_lcd ps input input input f6 c1 vss_mem vss_mem ps input input input f7 c2 vss_mem vss_mem ps input input input g7 f5 vss_mem vss_mem ps input input input h7 g6 vss_mem vss_mem ps input input input j7 h5 vss_mem vss_mem ps input input input k7 j6 vss_mem vss_mem ps input input input l7 k6 vss_mem vss_mem ps input input input m7 l6 vss_mem vss_mem ps input input input n7 n6 vss_mem vss_mem ps input input input p7 r6 vss_mem vss_mem ps input input input r7 t6 vss_mem vss_mem ps input input input t7 v6 vss_mem vss_mem ps input input input u7 y3 vss_mem vss_mem ps input input input r15 u20 vss_ulpi vss_ulpi ps input input input f17 g20 vss_msl vss_msl ps input input input e9 c10 vss_osc13m vss_osc13m ps input input input e11 c13 vss_pll vss_pll ps input input input e12 ad21 vss_pll vss_pll ps input input input w16 vss_pll vss_pll ps input input input table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 104 april 6, 2009 released 4.2.3 pxa30x processor pin use table 11 lists the mapping of signals to specific pxa30x processor package pins. note: 1. gpio reset/s3/d4/c4 operation: after any reset is asserted or if pxa31x processor is in s3/d4/c4 power mode, these pins are configured as the primary function of the mfp (generally as gpio input) and default pullup or pulldown occurs. 2. crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators and are not affected by either reset or s2/d3/c4 power mode. for more information, see the ?clocks control and power management? chapter in the pxa3xx processor family vol. i: system and timer configuration developers manual. 3. each mfp output value is based on mfprxx[sleep_sel], mfprxx[sleep_data], mfprxx[sleep_oe_n], mfprxx[pull_sel], mfprxx[pullup_en] and mfprxx[pulldown_en] following s2/d3/c4 wake-up. to prevent unnecessary current drain, ensure input signals are not floating during low-power modes. each gpio to be driven can be programmed to a 0/1 or be pulled up or pulled down during s2/d3/c4 power mode if the mvt and the io (hvt) supplies are present. 4. logic low when oscc[tensx] bit is cleared, clk_tout when oscc[tensx] is set. configure tens2 for s2/d3/c4 mode and tens3 for s3/d4/c4 power mode. 5. pulldown always enabled. 6. output functions during s2/d3/c4 power mode. 7. pullup always enabled. 8. pd-0 if up2ocr[dmpde] is set, then pd-0, hi-z if up2ocr[dmpde] is cleared. 9. hi-z if up2ocr[dppde] is cleared and up2ocr[dppue] is cleared; pu-1 if up2ocr[dppde] is cleared and up2ocr[dppue] is set; pd-0 if up2ocr[dppde] is set and up2ocr[dppue] is cleared. setting up2ocr[dppde] and up2ocr[dppue] at the same time is not allowed. 10. this signal?s pullup/pulldown is enabled during power-on, hardware, global watchdog and gpio resets. the pullup/pulldown must be disabled by software by setting pcfr[pudh] after the external devices driving these pins are configured. 11. there is no pullup or pulldown on this pin. asserts if pcfr[sl_rod] is clear. table 10: pxa31x processor pin usage summary (continued) 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c 4 power mode table 11: pxa30x pin usage summary 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode vcc_bbatt d6 b6 a6 clk_tout clk_tout oc clk-out 44 e7 b7 e6 ext_wake up0 ext_wakeup 0 icoc z pd-0 11 pd-0 11 pd-0 11 a5 c6 c6 nbatt_fau lt nbatt_fault ic input input input a7 e8 e9 ngpio_re set ngpio_reset ic pu-1 11 pu-1 11 pu-1 11 e8 d6 b6 nreset nreset ic input 7 input input d9 f9 a8 nreset_o ut nreset_out oc low 12 12 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 105 c5 a6 e5 ntrst ntrst ic input 7 input 7 input 7 a6 a7 a7 pwr_cap0 pwr_cap0 oa - - - e9 f8 f7 pwr_cap1 pwr_cap1 oa - - - e4 d3 c5 pwr_en pwr_en oc low low low b6 c7 b7 pwr_out pwr_out oa - - - b5 d4 f6 sys_en sys_en oc low low low e6 c4 a5 tck tck ic input input input e5 e3 b5 tdi tdi ic input 7 input 7 input 7 d5 d2 c4 tdo tdo ocz hi-z hi-z hi-z d4 c3 d3 tms tms ic input 7 input 7 input 7 d8 a8 c7 txtal_in txtal_in ia 22 2 c7 b8 c8 txtal_out txtal_out oa 22 2 vcc_mvt b8 b9 a9 pxtal_in pxtal_in ia 22 2 c8 c9 b9 pxtal_out pxtal_out oa 22 2 vcc_io1 b12 a11 a13 gpio0_2 gpio0_2 icoc z pd-0 1 float 1 3 a11 d11 a12 gpio1_2 gpio1_2 icoc z pd-0 1 float 1 3 e21 e18 d22 gpio91 gpio91 icoc z pu-1 1 float 1 3 d22 e21 c22 gpio92 gpio92 icoc z pu-1 1 float 1 3 c23 e20 e24 gpio93 gpio93 icoc z pd-0 1 float 1 3 e20 d21 c23 gpio94 gpio94 icoc z pd-0 1 float 1 3 d21 c20 d24 gpio95 gpio95 icoc z pd-0 1 float 1 3 c22 a19 b23 gpio96 gpio96 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 106 april 6, 2009 released c21 d20 a22 gpio97 gpio97 icoc z pd-0 1 float 1 3 d20 c21 c24 gpio98 gpio98 icoc z pd-0 1 float 1 3 e18 a18 b16 gpio99 gpio99 icoc z pd-0 1 float 1 3 b20 b18 a21 gpio100 gpio100 icoc z pd-0 1 float 1 3 a21 c19 b19 gpio101 gpio101 icoc z pu-1 1 float 1 3 a20 a17 a20 gpio102 gpio102 icoc z pu-1 1 float 1 3 b19 d18 c20 gpio103 gpio103 icoc z pu-1 1 float 1 3 d17 e19 c19 gpio104 gpio104 icoc z pu-1 1 float 1 3 c18 d17 f17 gpio105 gpio105 icoc z pu-1 1 float 1 3 a19 b17 b20 gpio106 gpio106 icoc z pu-1 1 float 1 3 c17 c16 a17 gpio107 gpio107 icoc z pu-1 1 float 1 3 b18 c17 c18 gpio108 gpio108 icoc z pu-1 1 float 1 3 a18 d16 f16 gpio109 gpio109 icoc z pd-0 1 float 1 3 b17 a16 a19 gpio110 gpio110 icoc z pu-1 1 float 1 3 c16 f14 e15 gpio111 gpio111 icoc z pu-1 1 float 1 3 a17 b15 h16 gpio112 gpio112 icoc z pd-0 1 float 1 3 e15 c15 b15 gpio113 gpio113 icoc z pd-0 1 float 1 3 b16 d15 e16 gpio114 gpio114 icoc z pu-1 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 107 a16 c13 a15 gpio115 gpio115 icoc z pd-0 1 float 1 3 c15 a14 a16 gpio116 gpio116 icoc z pd-0 1 float 1 3 b15 e14 e14 gpio117 gpio117 icoc z pd-0 1 float 1 3 c14 d14 c15 gpio118 gpio118 icoc z pd-0 1 float 1 3 d15 e13 b14 gpio119 gpio119 icoc z pd-0 1 float 1 3 a15 b14 f15 gpio120 gpio120 icoc z pd-0 1 float 1 3 b14 f13 e13 gpio121 gpio121 icoc z pd-0 1 float 1 3 a14 c14 f14 gpio122 gpio122 icoc z pd-0 1 float 1 3 d14 d13 b13 gpio123 gpio123 icoc z pu-1 1 float 1 3 b13 b12 f13 gpio124 gpio124 icoc z pd-0 1 float 1 3 a13 f12 f12 gpio125 gpio125 icoc z pd-0 1 float 1 3 c12 a12 a14 gpio126 gpio126 icoc z pu-1 1 float 1 3 a12 c12 c12 gpio127 gpio127 icoc z pu-1 1 float 1 3 a9 f10 a10 pwr_scl pwr_scl icoc z pu-1 11 pu-1 11 float 1 c10 b10 f11 pwr_sda pwr_sda icoc z pu-1 11 pu-1 11 float 1 a10 b11 h12 test test ic input 5 input 5 input 5 b10 f11 e10 testclk testclk ic input 5 input 5 input 5 e12 e10 b10 vctcxo_e n vctcxo_en oc low 66 c11 c11 b12 clk_pout clk_pout oc low float low table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 108 april 6, 2009 released vcc_df y5 aa4 ac4 df_addr0 df_addr0 ocz pd-0 1 float 1 3 y2 v6 ab5 df_addr1 df_addr1 ocz pd-0 1 float 1 3 y1 w6 ad4 df_addr2 df_addr2 ocz pd-0 1 float 1 3 y6 y4 ac5 df_addr3 df_addr3 ocz pd-0 1 float 1 3 aa1 aa5 y7 df_io0 df_io0 icoc z pd-0 1 float 1 3 aa3 aa6 ac7 df_io1 df_io1 icoc z pd-0 1 float 1 3 aa4 w7 ad6 df_io2 df_io2 icoc z pd-0 1 float 1 3 ab5 y8 ab9 df_io3 df_io3 icoc z pd-0 1 float 1 3 ac3 v10 ad12 df_io4 df_io4 icoc z pd-0 1 float 1 3 ac4 w13 ad13 df_io5 df_io5 icoc z pd-0 1 float 1 3 aa10 w12 ad14 df_io6 df_io6 icoc z pd-0 1 float 1 3 ab9 v11 y12 df_io7 df_io7 icoc z pd-0 1 float 1 3 aa2 u8 ad5 df_io8 df_io8 icoc z pd-0 1 float 1 3 y7 y5 ab8 df_io9 df_io9 icoc z pd-0 1 float 1 3 y8 y6 ad7 df_io10 df_io10 icoc z pd-0 1 float 1 3 ab4 w8 ad9 df_io11 df_io11 icoc z pd-0 1 float 1 3 ab8 u15 w13 df_io12 df_io12 icoc z pd-0 1 float 1 3 ac5 w10 ab12 df_io13 df_io13 icoc z pd-0 1 float 1 3 ac6 w11 y14 df_io14 df_io14 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 109 ac7 w15 ad15 df_io15 df_io15 icoc z pd-0 1 float 1 3 y3 v7 ac2 df_ale_n we df_ale ocz pu-1 1 float 1 3 ab6 v9 w10 df_ncs0 df_ncs0 ocz pu-1 1 float 1 3 ab10 u10 ac13 df_ncs1 df_ncs1 ocz pu-1 1 float 1 3 w4 w5 ab3 df_nre df_noe ocz pu-1 1 float 1 3 w3 w4 ab2 df_nwe df_nwe ocz pu-1 1 float 1 3 w2 w3 aa3 df_int_rn b df_rnb icz pu-1 1 float 1 3 ab3 v8 w6 df_cle_n oe nd_cle ocz pu-1 1 float 1 3 aa9 aa10 ac11 df_sclk_e df_sclk_e ocz pd-0 1 float 1 3 v1 v3 w1 gpio0 gpio0 icoc z pd-0 1 float 1 3 v2 u4 aa2 gpio1 gpio1 icoc z pu-1 1 float 1 3 v3 v1 y1 gpio2 gpio2 icoc z pu-1 1 float 1 3 w5 y3 ad3 nbe0 nbe0 ocz pu-1 1 float 1 3 y4 aa3 ac3 nbe1 nbe1 ocz pu-1 1 float 1 3 ab7 y10 ab11 nlla nlla ocz pu-1 1 float 1 3 aa8 y9 ad10 nlua nlua ocz pu-1 1 float 1 3 w1 w1 ab1 ncs0 ncs0 oc high high high u5 v4 aa1 ncs1 ncs1 oc high high high vcc_io3 ac15 w17 ac21 gpio17 gpio17 icoc z pd-0 1 float 1 3 ab15 w18 w17 gpio18 gpio18 icoc z pd-0 1 float 1 3 y16 u17 ab21 gpio19 gpio19 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 110 april 6, 2009 released ac16 v18 ab23 gpio20 gpio20 icoc z pu-1 1 float 1 3 ac17 w19 y22 gpio21 gpio21 icoc z pu-1 1 float 1 3 ab17 aa17 ac23 gpio22 gpio22 icoc z pu-1 1 float 1 3 aa17 y17 ab22 gpio23 gpio23 icoc z pu-1 1 float 1 3 y17 aa18 ad22 gpio24 gpio24 icoc z pd-0 1 float 1 3 w17 y18 aa23 gpio25 gpio25 icoc z pd-0 1 float 1 3 ac18 y19 aa24 gpio26 gpio26 icoc z pd-0 1 float 1 3 u19 v21 w19 gpio27 gpio27 icoc z pd-0 1 float 1 3 ac20 u21 y23 gpio28 gpio28 icoc z pd-0 1 float 1 3 ac21 v19 y24 gpio29 gpio29 icoc z pd-0 1 float 1 3 w20 v20 aa22 gpio30 gpio30 icoc z pd-0 1 float 1 3 y21 u18 w22 gpio31 gpio31 icoc z pd-0 1 float 1 3 ab21 u20 w23 gpio32 gpio32 icoc z pu-1 1 float 1 3 aa21 u19 w18 gpio33 gpio33 icoc z pu-1 1 float 1 3 aa22 t20 w24 gpio34 gpio34 icoc z pu-1 1 float 1 3 aa23 t18 v20 gpio35 gpio35 icoc z pu-1 1 float 1 3 v21 t21 v23 gpio36 gpio36 icoc z pu-1 1 float 1 3 y22 r17 v19 gpio37 gpio37 icoc z pu-1 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 111 y23 t17 u22 gpio38 gpio38 icoc z pd-0 1 float 1 3 ab18 e6 w15 gpio2_2 gpio2_2 icoc z pu-1 1 float 1 3 aa18 e5 w20 gpio3_2 gpio3_2 icoc z pd-0 1 float 1 3 y18 g8 y18 gpio4_2 gpio4_2 icoc z pd-0 1 float 1 3 ac19 f5 y20 gpio5_2 gpio5_2 icoc z pd-0 1 float 1 3 w18 e7 y19 gpio6_2 gpio6_2 icoc z pu-1 1 float 1 3 vcc_ci w22 r18 u19 gpio39 gpio39 icoc z pd-0 1 float 1 3 w23 t19 v24 gpio40 gpio40 icoc z pd-0 1 float 1 3 t20 r20 u23 gpio41 gpio41 icoc z pd-0 1 float 1 3 v22 r19 t22 gpio42 gpio42 icoc z pd-0 1 float 1 3 v23 p16 u24 gpio43 gpio43 icoc z pd-0 1 float 1 3 u21 r21 t20 gpio44 gpio44 icoc z pd-0 1 float 1 3 u22 p17 r20 gpio45 gpio45 icoc z pd-0 1 float 1 3 u23 p18 t17 gpio46 cif_dd7 icoc z pd-0 1 float 1 3 t21 n16 p22 gpio47 gpio47 icoc z pd-0 1 float 1 3 t22 p21 r19 gpio48 gpio48 icoc z pd-0 1 float 1 3 t23 n17 p20 gpio49 cif_mclk icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 112 april 6, 2009 released r21 n18 r24 gpio50 cif_pclk icoc z pd-0 1 float 1 3 r22 n19 n24 gpio51 cif_hsync icoc z pd-0 1 float 1 3 p20 m20 n20 gpio52 cif_vsync icoc z pd-0 1 float 1 3 vcc_lcd r23 m17 r23 gpio53 gpio53 icoc z pu-1 1 float 1 3 n20 m21 p23 gpio54 gpio54 icoc z pd-0 1 float 1 3 p21 m18 n22 gpio55 gpio55 icoc z pd-0 1 float 1 3 p22 l18 p24 gpio56 gpio56 icoc z pd-0 1 float 1 3 n19 m19 n23 gpio57 gpio57 icoc z pd-0 1 float 1 3 p23 l20 p19 gpio58 gpio58 icoc z pd-0 1 float 1 3 n21 l17 m19 gpio59 gpio59 icoc z pd-0 1 float 1 3 n22 l21 l19 gpio60 gpio60 icz pd-0 1 float 1 3 n23 k19 m22 gpio61 gpio61 icoc z pd-0 1 float 1 3 m23 l19 m23 gpio62 gpio62 icoc z pu-1 1 float 1 3 m21 k20 j19 gpio63 gpio63 icoc z pd-0 1 float 1 3 m22 k17 m24 gpio64 gpio64 icoc z pd-0 1 float 1 3 l21 j17 l22 gpio65 gpio65 icoc z pd-0 1 float 1 3 l23 k21 k22 gpio66 gpio66 icoc z pd-0 1 float 1 3 l20 j18 l23 gpio67 gpio67 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 113 l22 k18 l20 gpio68 gpio68 icoc z pd-0 1 float 1 3 l19 j19 k20 gpio69 gpio69 icoc z pd-0 1 float 1 3 k23 j20 l24 gpio70 gpio70 icoc z pd-0 1 float 1 3 k21 j16 h19 gpio71 gpio71 icoc z pd-0 1 float 1 3 k22 j21 k23 gpio72 gpio72 icoc z pd-0 1 float 1 3 j23 h16 k24 gpio73 gpio73 icoc z pd-0 1 float 1 3 j22 h17 j22 gpio74 gpio74 icoc z pd-0 1 float 1 3 j19 h18 g19 gpio75 gpio75 icoc z pd-0 1 float 1 3 j21 h20 j23 gpio76 gpio76 icoc z pd-0 1 float 1 3 vcc_mem e3 g3 f2 dqm0 dqm0 oc high high high t1 t4 u1 dqm1 dqm1 oc high high high d2 f3 g3 dqs0 dqs0 isoc z pd-0 pd-0 pd-0 t2 r4 v3 dqs1 dqs1 isoc z pd-0 pd-0 pd-0 l3 l3 m1 ma0 ma0 oc high high high n1 n4 r5 ma1 ma1 oc high high high j4 h3 h2 ma2 ma2 oc high high high n4 m1 p5 ma3 ma3 oc high high high h3 h4 k3 ma4 ma4 oc high high high m1 m3 p3 ma5 ma5 oc high high high h2 k4 j1 ma6 ma6 oc high high high m2 m2 n3 ma7 ma7 oc high high high table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 114 april 6, 2009 released h1 j1 k2 ma8 ma8 oc high high high m3 l2 n1 ma9 ma9 oc high high high l2 m4 n2 ma11 ma11 oc high high high j3 k3 l3 ma12 ma12 oc high high high l1 h5 m5 ma13 ma13 oc high high high g1 h2 j3 ma14 ma14 oc high high high g2 j4 j2 ma15 ma15 oc high high high d3 d1 d1 md0 md0 icso cz pd-0 pd-0 pd-0 c2 e1 e1 md1 md1 icso cz pd-0 pd-0 pd-0 c1 e2 e2 md2 md2 icso cz pd-0 pd-0 pd-0 g4 f1 f1 md3 md3 icso cz pd-0 pd-0 pd-0 f3 f2 g1 md4 md4 icso cz pd-0 pd-0 pd-0 e1 g1 g2 md5 md5 icso cz pd-0 pd-0 pd-0 f2 g2 h3 md6 md6 icso cz pd-0 pd-0 pd-0 f1 h1 h1 md7 md7 icso cz pd-0 pd-0 pd-0 r1 p3 t2 md8 md8 icso cz pd-0 pd-0 pd-0 r2 r3 t1 md9 md9 icso cz pd-0 pd-0 pd-0 r3 r1 u3 md10 md10 icso cz pd-0 pd-0 pd-0 r4 t2 u2 md11 md11 icso cz pd-0 pd-0 pd-0 t3 t1 v2 md12 md12 icso cz pd-0 pd-0 pd-0 u1 u2 v1 md13 md13 icso cz pd-0 pd-0 pd-0 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 115 u2 t3 w2 md14 md14 icso cz pd-0 pd-0 pd-0 u3 u1 w3 md15 md15 icso cz pd-0 pd-0 pd-0 n3 n3 t3 nsdcas nsdcas oc high high high k1 l1 m3 nsdcs0 nsdcs0 oc high high high k2 j2 m2 nsdcs1 nsdcs1 oc high high high n2 p2 p2 nsdras nsdras oc high high high p1 p1 r3 nsdwe nsdwe oc high high high n5 n1 p1 rcomp_dd r rcomp_ddr oa - - - p2 r2 r2 sdcke sdcke oc low low low k3 k1 l1 sdclk0 sdclk0 oc low low low k4 k2 l2 sdclk1 sdclk1 oc high high high k5 j3 k1 sdma10 sdma10 oc high high high vcc_msl h23 h19 h22 gpio77 gpio77 icoc z pd-0 1 float 1 3 h22 g16 j24 gpio78 gpio78 icoc z pd-0 1 float 1 3 j20 f16 j20 gpio79 gpio79 icoc z pd-0 1 float 1 3 g23 h21 h23 gpio80 gpio80 icoc z pd-0 1 float 1 3 g22 g18 g23 gpio81 gpio81 icoc z pd-0 1 float 1 3 h21 g20 g22 gpio82 gpio82 icoc z pd-0 1 float 1 3 f23 g19 f23 gpio83 gpio83 icoc z pd-0 1 float 1 3 g21 g21 f20 gpio84 gpio84 icoc z pu-1 1 float 1 3 f22 f19 f22 gpio85 gpio85 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 116 april 6, 2009 released e23 e16 h24 gpio86 gpio86 icoc z pd-0 1 float 1 3 e22 f18 e23 gpio87 gpio87 icoc z pd-0 1 float 1 3 f21 f20 e22 gpio88 gpio88 icoc z pd-0 1 float 1 3 f20 e17 g24 gpio89 gpio89 icoc z pu-1 1 float 1 3 d23 f21 d23 gpio90 gpio90 icoc z pu-1 1 float 1 3 vcc_usb a3 a5 c3 usbh1_n usbh1_n iaoa pd-0 8 pd-0 8 pd-0 8 a4 b5 b4 usbh1_p usbh1_p iaoa pd-0 8 pd-0 8 pd-0 8 c3 a3 b3 usbotg_n usbotg_n iaoa hi-z hi-z or pd-0 9 hi-z or pd-0 9 b3 a4 a3 usbotg_p usbotg_p iaoa hi-z hi-z or pd-0 or pu-1 8 , 10 hi-z or pd-0 or pu-1 8 , 10 vcc_card1 aa11 u11 ab14 gpio3 gpio3 icoc z pd-0 1 float 1 3 ac8 aa11 ac14 gpio4 gpio4 icoc z pd-0 1 float 1 3 ab11 v12 ab15 gpio5 gpio5 icoc z pd-0 1 float 1 3 ac9 v13 ad17 gpio6 gpio6 icoc z pu-1 1 float 1 3 ac10 w14 ab17 gpio7 gpio7 icoc z pd-0 1 float 1 3 aa13 u14 y16 gpio8 gpio8 icoc z pd-0 1 float 1 3 vcc_card2 ac11 u12 ad16 gpio9 gpio9 icoc z pd-0 1 float 1 3 ac12 y14 ab18 gpio10 gpio10 icoc z pd-0 1 float 1 3 table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 117 ab13 v14 ab19 gpio11 gpio11 icoc z pd-0 1 float 1 3 ac13 u16 ac20 gpio12 gpio12 icoc z pu-1 1 float 1 3 ab14 v15 ac19 gpio13 gpio13 icoc z pd-0 1 float 1 3 ac14 y15 ad20 gpio14 gpio14 icoc z pd-0 1 float 1 3 y15 y16 y17 gpio15 gpio15 icoc z pu-1 1 float 1 3 aa15 v16 ad19 gpio16 gpio16 icoc z pu-1 1 float 1 3 rfu balls p4 j8 e18 rfu_p4/ rfu_j8/ rfu_e18 b21 k8 e20 rfu_b21/ rfu_k8/ rfu_e20 c19 n2 f18 rfu_c19/ rfu_n2/ rfu_f18 c20 n8 f19 rfu_c20/ rfu_n8/ rfu_f19 d18 p8 n17 rfu_d18/ rfu_p8/ rfu_n17 ????? r15 p17 rfu_r15/r fu_p17 ????? r16 r1 rfu_r16/r fu_r1 ????? v17 u17 rfu_v17/r fu_u17 ????? w9 ad11 rfu_w9/rf u_ad11 ????? w20 rfu_w20 ? ? ? ? ? table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 118 april 6, 2009 released w21 rfu_w21 ? ? ? ? ? no connect (nc) balls a1 b4 a1 nc ? ? ? ? ? a2 c1 a2 nc ? ? ? ? ? b1 c5 a23 nc ? ? ? ? ? b2 d19 a24 nc ? ? ? ? ? a22 g4 b1 nc ? ? ? ? ? a23 l4 b24 nc ? ? ? ? ? b22 l8 e17 nc ? ? ? ? ? b23 m8 e19 nc ? ? ? ? ? v19 p4 w5 nc ? ? ? ? ? v20 p5 w7 nc ? ? ? ? ? w10 u3 w8 nc ? ? ? ? ? w19 v2 w9 nc ? ? ? ? ? y19 u13 w12 nc ? ? ? ? ? y20 w2 y9 nc ? ? ? ? ? aa19 aa19 ab6 nc ? ? ? ? ? aa20 ac1 nc ? ? ? ? ? ab19 ac6 nc ? ? ? ? ? ab20 ac24 nc ? ? ? ? ? ab1 ad1 nc ? ? ? ? ? ab2 ad2 nc ? ? ? ? ? ac1 ad23 nc ? ? ? ? ? ac2 ad24 nc ? ? ? ? ? ab22 nc ? ? ? ? ? ab23 nc ? ? ? ? ? ac22 nc ? ? ? ? ? ac23 nc ? ? ? ? ? table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 119 aa5 nc ? ? ? ? ? internal nand signals u5 df_nwp df_nwp input input input input power supplies e11 a10 b17 vcc_apps vcc_apps ps input input input e14 a13 c14 vcc_apps vcc_apps ps input input input l4 a15 e11 vcc_apps vcc_apps ps input input input r20 h10 h10 vcc_apps vcc_apps ps input input input w9 h11 h15 vcc_apps vcc_apps ps input input input w13 h12 k8 vcc_apps vcc_apps ps input input input y12 k14 k17 vcc_apps vcc_apps ps input input input l5 l5 vcc_apps vcc_apps ps input input input l14 r8 vcc_apps vcc_apps ps input input input m14 r17 vcc_apps vcc_apps ps input input input n5 t24 vcc_apps vcc_apps ps input input input n21 u10 vcc_apps vcc_apps ps input input input p10 u15 vcc_apps vcc_apps ps input input input p11 ab16 vcc_apps vcc_apps ps input input input p12 ac9 vcc_apps vcc_apps ps input input input y13 vcc_apps vcc_apps ps input input input aa7 vcc_apps vcc_apps ps input input input aa9 vcc_apps vcc_apps ps input input input aa12 vcc_apps vcc_apps ps input input input d7 c8 e8 vcc_bbat t vcc_bbatt ps input input input b9 d10 c9 vcc_bg vcc_bg ps input input input aa12 y11 ac15 vcc_card 1 vcc_card1 ps input input input y14 aa14 ad18 vcc_card 2 vcc_card2 ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 120 april 6, 2009 released r19 p15 r22 vcc_ci vcc_ci ps input input input p20 vcc_ci vcc_ci ps input input input v4 g11 y6 vcc_df vcc_df ps input input input w6 t9 ab4 vcc_df vcc_df ps input input input w8 t10 ab7 vcc_df vcc_df ps input input input y11 t11 ab10 vcc_df vcc_df ps input input input t12 ab13 vcc_df vcc_df ps input input input t13 ac12 vcc_df vcc_df ps input input input b11 e15 a11 vcc_io1 vcc_io1 ps input input input e16 g10 c16 vcc_io1 vcc_io1 ps input input input f19 g15 f24 vcc_io1 vcc_io1 ps input input input w21 v22 vcc_io3 vcc_io3 ps input input input aa16 t16 ab20 vcc_io3 vcc_io3 ps input input input k19 k16 k19 vcc_lcd vcc_lcd ps input input input m19 l16 vcc_lcd vcc_lcd ps input input input m16 vcc_lcd vcc_lcd ps input input input d1 d5 d2 vcc_mem vcc_mem ps input input input g3 g5 e3 vcc_mem vcc_mem ps input input input g5 g6 f3 vcc_mem vcc_mem ps input input input j1 h6 g5 vcc_mem vcc_mem ps input input input m5 j6 j5 vcc_mem vcc_mem ps input input input r5 k6 k5 vcc_mem vcc_mem ps input input input t5 l6 n5 vcc_mem vcc_mem ps input input input m6 t5 vcc_mem vcc_mem ps input input input n6 v5 vcc_mem vcc_mem ps input input input p6 y2 vcc_mem vcc_mem ps input input input r6 vcc_mem vcc_mem ps input input input t6 vcc_mem vcc_mem ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 121 u6 vcc_mem vcc_mem ps input input input v5 vcc_mem vcc_mem ps input input input h20 g17 h20 vcc_msl vcc_msl ps input input input d10 e4 b18 vcc_mvt vcc_mvt ps input input input e17 g9 c21 vcc_mvt vcc_mvt ps input input input g20 g14 f9 vcc_mvt vcc_mvt ps input input input h5 h15 h6 vcc_mvt vcc_mvt ps input input input p3 j5 n19 vcc_mvt vcc_mvt ps input input input p19 j15 p6 vcc_mvt vcc_mvt ps input input input w14 n15 u6 vcc_mvt vcc_mvt ps input input input aa7 r14 w16 vcc_mvt vcc_mvt ps input input input t5 ac8 vcc_mvt vcc_mvt ps input input input u9 vcc_mvt vcc_mvt ps input input input a8 d9 b8 vcc_osc1 3m vcc_osc13m ps input input input c13 d12 c11 vcc_pll vcc_pll ps input input input w16 aa16 ac22 vcc_pll vcc_pll ps input input input d19 b19 b21 vcc_sram vcc_sram ps input input input y9 c18 w11 vcc_sram vcc_sram ps input input input aa8 vcc_sram vcc_sram ps input input input b4 b3 a4 vcc_usb vcc_usb ps input input input j9 a9 c17 vss vss ps input input input j10 a20 e7 vss vss ps input input input j11 a21 e12 vss vss ps input input input j12 b13 h8 vss vss ps input input input j13 b16 h9 vss vss ps input input input j14 b20 h11 vss vss ps input input input j15 b21 h13 vss vss ps input input input e10 c2 h14 vss vss ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 122 april 6, 2009 released e13 f4 h17 vss vss ps input input input g19 h8 j8 vss vss ps input input input j5 h9 j17 vss vss ps input input input l5 h13 l8 vss vss ps input input input k9 h14 l17 vss vss ps input input input k10 j14 m6 vss vss ps input input input k11 k5 m8 vss vss ps input input input k12 m5 m17 vss vss ps input input input k13 n14 n8 vss vss ps input input input k14 n20 p8 vss vss ps input input input k15 p9 t8 vss vss ps input input input l9 p13 t23 vss vss ps input input input l10 p14 u5 vss vss ps input input input l11 r5 u8 vss vss ps input input input l12 r8 u9 vss vss ps input input input l13 t8 u11 vss vss ps input input input l14 t14 u12 vss vss ps input input input l15 y7 u13 vss vss ps input input input m9 aa13 u14 vss vss ps input input input m10 d7 u16 vss vss ps input input input m11 ac10 vss vss ps input input input m12 ac16 vss vss ps input input input m13 ac17 vss vss ps input input input m14 ad8 vss vss ps input input input m15 vss vss ps input input input n9 vss vss ps input input input n10 vss vss ps input input input n11 vss vss ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 123 n12 vss vss ps input input input n13 vss vss ps input input input n14 vss vss ps input input input n15 vss vss ps input input input p9 vss vss ps input input input p10 vss vss ps input input input p11 vss vss ps input input input p12 vss vss ps input input input p13 vss vss ps input input input p14 vss vss ps input input input p15 vss vss ps input input input r9 vss vss ps input input input r10 vss vss ps input input input r11 vss vss ps input input input r12 vss vss ps input input input r13 vss vss ps input input input r14 vss vss ps input input input r15 vss vss ps input input input w12 vss vss ps input input input y10 vss vss ps input input input aa6 vss vss ps input input input y13 vss vss ps input input input c6 vss vss ps input input input b7 d8 f8 vss_bbatt vss_bbatt ps input input input d11 c10 f10 vss_bg vss_bg ps input input input aa14 y12 y15 vss_card 1 vss_card1 ps input input input ab12 vss_card 1 vss_card1 ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 124 april 6, 2009 released aa15 ac18 vss_card 2 vss_card2 ps input input input t19 p19 t19 vss_ci vss_ci ps input input input v5 g12 w14 vss_df vss_df ps input input input w7 r9 y5 vss_df vss_df ps input input input w11 r10 y8 vss_df vss_df ps input input input r11 y10 vss_df vss_df ps input input input r12 y11 vss_df vss_df ps input input input r13 y13 vss_df vss_df ps input input input y1 vss_df vss_df ps input input input y2 vss_df vss_df ps input input input aa1 vss_df vss_df ps input input input aa2 vss_df vss_df ps input input input d12 f15 a18 vss_io1 vss_io1 ps input input input d16 g13 b11 vss_io1 vss_io1 ps input input input e19 b22 vss_io1 vss_io1 ps input input input u20 t15 u20 vss_io3 vss_io3 ps input input input ab16 y20 ab24 vss_io3 vss_io3 ps input input input y21 vss_io3 vss_io3 ps input input input aa20 vss_io3 vss_io3 ps input input input aa21 vss_io3 vss_io3 ps input input input k20 k15 m20 vss_lcd vss_lcd ps input input input m20 l15 vss_lcd vss_lcd ps input input input m15 vss_lcd vss_lcd ps input input input e2 f6 c1 vss_mem vss_mem ps input input input f4 f7 c2 vss_mem vss_mem ps input input input f5 g7 f5 vss_mem vss_mem ps input input input h4 h7 g6 vss_mem vss_mem ps input input input j2 j7 h5 vss_mem vss_mem ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 125 m4 k7 j6 vss_mem vss_mem ps input input input p5 l7 k6 vss_mem vss_mem ps input input input t4 m7 l6 vss_mem vss_mem ps input input input u4 n7 n6 vss_mem vss_mem ps input input input p7 r6 vss_mem vss_mem ps input input input r7 t6 vss_mem vss_mem ps input input input t7 v6 vss_mem vss_mem ps input input input u7 y3 vss_mem vss_mem ps input input input h19 f17 g20 vss_msl vss_msl ps input input input c9 e9 c10 vss_osc1 3m vss_osc13m ps input input input d13 e11 c13 vss_pll vss_pll ps input input input w15 e12 ad21 vss_pll vss_pll ps input input input w16 vss_pll vss_pll ps input input input c4 a1 b2 vss_usb vss_usb ps input input input a2 vss_usb vss_usb ps input input input b1 vss_usb vss_usb ps input input input b2 vss_usb vss_usb ps input input input table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 126 april 6, 2009 released 4.2.4 signal type definitions table 12 contains the signal type definitions for ta bl e 9 , ta b l e 1 0 and tab l e 11 . 1. gpio reset/s3 operation: after any reset is asserted or if pxa30x processor is in s3/d4/c4 power mode, these pins are configured as the primary function of the mfp (generally as gpio input) and default pullup or pulldown occurs. 2. crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators and are not affected by either reset or s2/d3/c4 power mode. for more information, for more information, see the ?clocks control and power management? chapter in the pxa3xx processor family vol. i: system and timer configuration developers manual. 3. each mfp output value is based on mfprxx[sleep_sel], mfprxx[sleep_data], mfprxx[sleep_oe_n], mfprxx[pull_sel], mfprxx[pullup_en] and mfprxx[pulldown_en] following s2/d3/c4 wake-up. to prevent unnecessary current drain, ensure input signals are not floating during low-power modes. each gpio to be driven can be programmed to a 0/1 or be pulled up or pulled down during s2/d3/c4 power mode if the mvt and the io (hvt) supplies are present. 4. logic low when oscc[tensx] bit is cleared, clk_tout when oscc[tensx] is set. configure tens2 for s2/d3/c4 mode and tens3 for s3/d4/c4 power mode. 5. pulldown always enabled. 6. output functions during s2/d3/c4 power mode. 7. pullup always enabled. 8. 20 k nominal, 14.5 k min - 24.5 k max 9. pd-0 if up2ocr[dmpde] is set, then pd-0, hi-z if up2ocr[dmpde] is cleared. 10. hi-z if up2ocr[dppde] is cleared and up2ocr[dppue] is cleared; pu-1 if up2ocr[dppde] is cleared and up2ocr[dppue] is set; pd-0 if up2ocr[dppde] is set and up2ocr[dppue] is cleared. setting up2ocr[dppde] and up2ocr[dppue] at the same time is not allowed. 11. this signal?s pullup/pulldown is enabled during power-on, hardware, global watchdog and gpio resets. the pullup/pulldown must be disabled by software by setting pcfr[pudh] after the external devices driving these pins are configured. 12. there is no pullup or pulldown on this pin. asserts if pcfr[sl_rod] is clear. table 11: pxa30x pin usage summary (continued) 19mm 2 ball # 15mm 2 ball # 13mm 2 ball # ball name function after reset type reset state s3/d4/c4 power mode s2/d3/c4 power mode table 12: signal types abbreviation type description abbreviation type description ic cmos input isocz sstl input, cmos output, three-stateable oc cmos output oa analog output ocz cmos output, three-stateable iaoa analog bidirectional icocz cmos bidirectional, three-stateable iao az analog bidirectional - three-stateable ia analog input ps power supply os sstl output is sstl input icsocz cmos or sstl input, cmos output, three-stateable www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 127 5 maximum ratings and operation conditions 5.1 absolute maximum ratings the absolute maximum ratings (shown in table 13 ) define limitations for electrical and thermal stresses. these limits prevent permanent damage to the pxa3xx processor family. note absolute maximum ratings are not operating ranges. operation at absolute maximum ratings is not guaranteed. table 13: absolute maximum ratings symbol description min max units t s storage temperature ?40 125 c voltage applied to vcc_bbatt 2.0 4.0 v v cc_hv voltage applied to high-voltage supply pins vcc_msl, vcc_card2, vcc_card1, vcc_io1, vcc_ci, vcc_df, vcc_lcd).vcc_io3 vss?0.3 vss+4.0 v vcc_io4, vcc_io6, vcc_tsi (pxa32x only) v vcc_usb (pxa32x and pxa30x only) v vcc_bias (pxa31x only) v vcc_ulpi (pxa31x only) vss?0.3 vss+2.0 v v cc_mv voltage applied to low-voltage supply pins (vcc_mvt, vcc_bg, vcc_pll, vcc_osc13m, vcc_mem) vss?0.3 vss+2.0 v v cc_lv voltage applied to low-voltage supply pins (vcc_apps, vcc_sram) vss?0.3 vss+1.54 v v ip voltage applied to non-supply pins except pxtal_in, pxtal_out, txtal_in, and txtal_out pins vss?0.3 vss+4.0 v v ip_x voltage applied to xtal pins (pxtal_in, pxtal_out, txtal_in, txtal_out) vss?0.3 vss+1.9 v www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 128 april 6, 2009 released 5.2 operating conditions this section discusses operating voltage, frequency, and temperature specifications for the pxa3xx processor family. table 14 shows each power domains supported voltages. tab le 1 4 also shows the application core frequency and supply voltage operating ranges for vcc_sram and vcc_apps of the pxa32x processor, pxa31x processor and the pxa30x processor. each frequency range is specified in one of the following formats: (turbo frequency / run frequency / internal switch bus frequency / internal system bus frequency) or (turbo frequency / run frequency / internal switch bus frequency / internal system bus frequency / sram frequency) or (power mode (sx/dx/cx) / sram frequency (optional)) refer to the ?clocks controller and power management unit? chapter of the pxa3xx processor family vol. i: system and timer configuration developers manual for supported frequencies and clock-register settings as listed in ta bl e 1 4 . v esd maximum esd stress voltage, three stresses maximum: ? any pin to any supply pin, either polarity, or ? any pin to all non-supply pins together, either polarity hbm 1 ? 2000 v cdm 2 ?700v i eos maximum dc input current (electrical overstress) for any non-supply pin ?5 ma note: 1. hbm = human body model 2. cdm = charge device model table 13: absolute maximum ratings (continued) symbol description min max units table 14: voltage, temperature, and frequency electrical specifications symbol description min typical max units notes operating temperature tcase package operating temperature (standard temp) -25 ? +85 c 1 tcase package operating temperature (extended temp) (pxa32x only) -40 ? +85 c 1 theta jc junction-to-case temperature gradient (vf-bga) ? 2.00 ? c / watt ? vcc_bbatt voltage vccbatt voltage applied on vcc_bbatt 2.40 3.00 3.60 v ? www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 129 tbbattramp ramp rate 5.0 v/ s ? 20.00 v/ s? vcc_mvt voltage vccmvt_0 voltage applied on vcc_mvt in s3/d4/c4 ? 0 ? v ? vccmvt_1 voltage applied on vcc_mvt 1.70 1.80 1.90 v ? vccmvt_2 voltage applied on vcc_mvt 1.80 1.90 2.00 v 3 tsysramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_bg voltage vccbg_0 voltage applied on vcc_bg in s3/d4/c4 ? 0 ? v ? vccbg_1 voltage applied on vcc_bg 1.70 1.80 1.90 v ? vccbg_2 voltage applied on vcc_bg 1.80 1.90 2.00 v 3 tsysramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_pll voltage vccpll_0 voltage applied on vcc_pll in s3/d4/c4 ? 0 ? v ? vccpll_1 voltage applied on vcc_pll 1.70 1.80 1.90 v ? vccpll_2 voltage applied on vcc_pll 1.80 1.90 2.00 v 3 tsysramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_osc13m voltage vccosc13m_0 voltage applied on vcc_osc13m in s3/d4/c4 ?0 ?v ? vccosc13m_1 voltage applied on vcc_osc13m 1.70 1.80 1.90 v ? vccosc13m_2 voltage applied on vcc_osc13m 1.80 1.90 2.00 v 3 tsysramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_apps voltage at frequency ranges (turbo/run/switch/system bus), (power mode (sx/dx/cx)) (standard bin only) vccapps_0 voltage applied on vcc_apps in s3/d4/c4, s2/d3/c4 ?0?v? vccapps_1 voltage applied on vcc_apps at s0/d0cs/c0, 104/104/104/104, 208/208/208/104 1.05 1.10 1.2 v 2 , 5 vccapps_2 voltage applied on vcc_apps at 416/208/208/156 1.05 1.10 1.2 v 2 table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 130 april 6, 2009 released vccapps_3 voltage applied on vcc_apps at 624/312/312/208 1.31 1.375 1.475 v 2 vccapps_4 voltage applied on vcc_apps in s0/d2/c2 , s0/d1/c2 or at 806/403/403/208 7 1.33 1.40 1.50 v 2 tpwrramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_sram voltage at frequency range (turbo/run/switch/system bus/sram), (power mode (sx/dx/cx) @ sram frequency) (standard bin only) vccsram_0 voltage applied on vcc_sram in s3/d4/c4 or s2/d3/c4 ?0 ?v ? vccsram_1 voltage applied on vcc_sram at s0/d0cs/c0 , 104/104/104/104 or 208/208/208/104 1.05 1.10 1.20 v 2 , 5 vccsram_2 voltage applied on vcc_sram at 416/208/208/156 1.05 1.10 1.2 v 2 vccsram_3 voltage applied on vcc_sram at 624/312/312/208 1.31 1.375 1.475 v 2 , 5 vccsram_4 voltage applied on vcc_sram in s2/d3/c4 4 , s0/d2/c2 , s0/d1/c2 , or 806/403/403/208 7 1.33 1.40 1.5 v 2 , 5 tpwrramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_apps voltage at frequency ranges (turbo/run/switch/system bus), (power mode (sx/dx/cx)) (low power bin only) vccapps_0 voltage applied on vcc_apps in s3/d4/c4 , or s2/d3/c4 ?0 ?v ? vccapps_1 voltage applied on vcc_apps at s0/d0cs/c0, 104/104/104/104, 208/208/208/104 0.975 1.00 1.10 v 2 , 5 vccapps_2 voltage applied on vcc_apps at 416/208/208/156 1.05 1.10 1.2 v 2 vccapps_3 voltage applied on vcc_apps at 624/312/312/208 1.31 1.375 1.475 v 2 vccapps_4 voltage applied on vcc_apps in s0/d2/c2, s0/d1/c2 or at 806/403/403/208 7 1.33 1.40 1.50 v 2 tpwrramp ramp rate 2.00 10.00 12.00 mv/ s? vcc_sram voltage at frequency range (turbo/run/switch/system bus/sram), (power mode (sx/dx/cx) @ sram frequency) (low power bin only) vccsram_0 voltage applied on vcc_sram in s3/d4/c4 or s2/d3/c4 ?0 ?v ? table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 131 vccsram_1 voltage applied on vcc_sram at s0/d0cs/c0, 104/104/104/104 or 208/208/208/104 0.975 1.00 1.20 v 2 , 5 vccsram_2 voltage applied on vcc_sram at 416/208/208/156 1.05 1.10 1.2 v 2 vccsram_3 voltage applied on vcc_sram at 624/312/312/208 1.31 1.375 1.475 v 2 , 5 vccsram_4 voltage applied on vcc_sram in s2/d3/c4 4 , s0/d2/c2, s0/d1/c2 or at 806/403/403/208 7 1.33 1.40 1.5 v 2 , 5 tpwrramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_mem voltage vccmem_0 voltage applied on vcc_mem in s3/d4/c4 ? 0 ? v ? vccmem_1 voltage applied on vcc_mem 1.70 1.80 1.90 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_io1 voltage vccio1_0 voltage applied on vcc_io1 in s3/d4/c4 ? 0 ? v ? vccio1_1 voltage applied on vcc_io1 1.70 1.80 1.98 v ? vccio1_2 voltage applied on vcc_io1 2.70 3.00 3.30 v ? vccio1_3 voltage applied on vcc_io1 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_io3 voltage vccio3_0 voltage applied on vcc_io3 in s3/d4/c4 ? 0 ? v ? vccio3_1 voltage applied on vcc_io3 1.70 1.80 1.98 v ? vccio3_2 voltage applied on vcc_io3 2.70 3.00 3.30 v ? vccio3_3 voltage applied on vcc_io3 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_io4 voltage (pxa32x only) vccio4_0 voltage applied on vcc_io4 in s3/d4/c4 ?0 ?v ? vccio4_1 voltage applied on vcc_io4 1.70 1.80 1.98 v ? vccio4_2 voltage applied on vcc_io4 2.70 3.00 3.30 v ? vccio4_3 voltage applied on vcc_io4 2.97 3.30 3.63 v ? table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 132 april 6, 2009 released tsysramp ramp rate ? 10.00 12.00 mv/ s ? vcc_io6 voltage (pxa32x only) vccio6_0 voltage applied on vcc_io6 in s3/d4/c4 ?0 ?v ? vccio6_1 voltage applied on vcc_io6 1.70 1.80 1.98 v ? vccio6_2 voltage applied on vcc_io6 2.70 3.00 3.30 v ? vccio6_3 voltage applied on vcc_io6 2.97 3.30 3.63 v ? tsysramp ramp rate ? 10.00 12.00 mv/ s ? vcc_msl voltage vccmsl_0 voltage applied on vcc_msl in s3/d4/c4 ? 0 ? v ? vccmsl_1 voltage applied on vcc_msl 1.70 1.80 1.98 v ? vccmsl_2 voltage applied on vcc_msl 2.70 3.00 3.30 v ? vccmsl_3 voltage applied on vcc_msl 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_lcd voltage vcclcd_0 voltage applied on vcc_lcd in s3/d4/c4 ? 0 ? v ? vcclcd_1 voltage applied on vcc_lcd 1.70 1.80 1.98 v ? vcclcd_2 voltage applied on vcc_lcd 2.70 3.00 3.30 v ? vcclcd_3 voltage applied on vcc_lcd 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_bias voltage (pxa310 only) vccbias_0 voltage applied on vcc_bias in s3/d4/c4 ? 0 ? v ? vccbias_1 voltage applied on vcc_bias 1.80 3.30 3.6 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_usb voltage (pxa32x and pxa30x only) vccusb_0 voltage applied on vcc_usb in s3/d4/c4 ? 0 ? v ? vccusb_1 voltage applied on vcc_usb 3.00 3.30 3.6 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_ulpi voltage (pxa31x only) table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 133 vcculpi_0 voltage applied on vcc_ulpi in s3/d4/c4 ? 0 ? v ? vcculpi_1 voltage applied on vcc_ulpi 1.70 1.80 1.98 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_card1 voltage vcccard1_0 voltage applied on vcc_card1 in s3/d4/c4 ? 0 ? v ? vcccard1_1 voltage applied on vcc_card1 1.70 1.80 1.98 v ? vcccard1_2 voltage applied on vcc_card1 2.70 3.00 3.30 v ? vcccard1_3 voltage applied on vcc_card1 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_card2 voltage vcccard2_0 voltage applied on vcc_card2 in s3/d4/c4 ? 0 ? v ? vcccard2_1 voltage applied on vcc_card2 1.70 1.80 1.98 v ? vcccard2_2 voltage applied on vcc_card2 2.70 3.00 3.30 v ? vcccard2_3 voltage applied on vcc_card2 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_df voltage vccdf_0 voltage applied on vcc_df in s3/d4/c4 ? 0 ? v ? vccdf_1 voltage applied on vcc_df 1.70 1.80 1.98 v ? vccdf_2 voltage applied on vcc_df 2.70 3.00 3.30 v ? vccdf_3 voltage applied on vcc_df 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_ci voltage vccci_0 voltage applied on vcc_ci in s3/d4/c4 ? 0 ? v ? vccci_1 voltage applied on vcc_ci 1.70 1.80 1.98 v ? vccci_2 voltage applied on vcc_ci 2.70 3.00 3.30 v ? vccci_3 voltage applied on vcc_ci 2.97 3.30 3.63 v ? tsysramp ramp rate 2.00 10.00 12.00 mv/ s 6 vcc_tsi voltage (pxa32x only) table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 134 april 6, 2009 released vcctsi_0 voltage applied on vcc_tsi in s3/d4/c4 ?0 ?v ? vcctsi_1 voltage applied on vcc_tsi 2.97 3.30 3.63 v ? tsysramp ramp rate ? 10.00 12.00 mv/ s ? note: 1. system design must ensure that the device case temperature is maintained within the specified limits. in some system applications it may be necessary to use external thermal management (for example, a package-mounted heat spreader) or configure the device to limit power consumption and maintain acceptable case temperatures. 2. the voltage ranges specified for vcc_apps and vcc_sram are the targeted voltage ranges for the product. these ranges may extend or narrow depending on actual product performance and product skews. marvell recommends that extended voltage and current capabilities be designed into the power management ic to accommodate future changes to this specification without requiring changes to the power management ic. 3. vcc_mvt requires the capability to increase from the normal operating voltage of 1.8 v to 1.9 v during certain times. this increased voltage is required under certain conditions, not during normal operation. when vcc_mvt is raised to 1.9 v, it is operating in ?boost mode?. boost mode is only used during factory programming. if vcc_pll, vcc_osc13m and vcc_bg are supplied by the same pmic supply, which is the method marvell recommends, these other voltages also operate at 1. 9 v. maximum current capabilities and voltage tolerances are identical in boost mode and normal operation. 4. this option allows one or more 128 kbyte sram banks to retain state during s2/d3/c4 mode. 5. reset voltage for vcc_apps and vcc_sram is 1.4 v and the startup frequency is 104/104/104/104 mhz. 6. min ramp rate = (maximum voltage transition) / (lpm_del - ((power i2c command execution time)) 7. pxa32x only table 14: voltage, temperature, and frequency electrical specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 135 6 electrical specifications this chapter includes dc voltage and current characteristics as well as crystal and oscillator specifications for the pxa3xx processor family. 6.1 dc voltage and current characteristics the dc characteristics for each pin include input-sense levels, output-drive levels, current and pullup/down resistive values. these parameters can be used to determine maximum dc loading and to determine maximum transition times for a given load. table 15 shows the dc operating conditions for the input, output, and i/o pins used by the empi bus controlled by the dmemc. ta bl e 1 6 applies to all signals powered by vcc_high. vcc_high is not a physical supply on the pxa3xx processors, but the term used to refer to the collective groups of high voltage supplies which consist of vcc_io1, vcc_io3, vcc_io4 (pxa32x only), vcc_io6 (pxa32x only), vcc_df, vcc_ci, vcc_card1, vcc_card2, vcc_lcd, vcc_usb (pxa32x and pxa30x only), vcc_bias (pxa31x only), vcc_ulpi (pxa31x only) and vcc_msl. table 15: ddr input, output, and i/o pins ac/dc operating conditions symbols description min typical max unit notes input dc operating conditions (sstl receiver) 1 vih (dc) input high voltage 0.7 * vcc_mem ? vcc_mem + 0.3 v 2 v il(dc) input low voltage -0.3 ? 0.3 * vcc_mem v 2 vih (ac) input high voltage 0.8 * vcc_mem ? vcc_mem + 0.3 v? v il(ac) input low voltage -0.3 ? 0.2 * vcc_mem v? r pullup pullup resistance 65 3 100 160 4 k 5 , 6 r pulldown pulldown resistance 55 3 100 175 4 k 5 , 6 output dc operating conditions (vcc_mem = 1.8 v) v oh high-level output voltage absolute load current achieving voh 0.9 * vcc_mem ? vcc_mem v i oh = (min) -6.5 ma v ol low-level output voltage absolute load current achieving vol vss ? 0.1 * vcc_mem vi ol = (min) 6.5 ma www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 136 april 6, 2009 released note: 1. use values when sstl (differential) receiver is enabled. see empi[sstl_dmem_en] and empi[sst_smem_en] register definitions in the pxa3xx processor family vol. ii: memory controller configuration developers manual . 2. the schmidt trigger must be disabled for sstl mode. empi[schm_dmem_en] must be cleared. register definitions are found in the pxa3xx processor family vol. ii: memory controller configuration developers manual . 3. max voltage, minimum temperature 4. min voltage, maximum temperature 5. enabled during reset, s2/d3/c4 power state, and s3/d4/c4 power mode. not enabled through software control. 6. enabled and disabled using empi[pw_dqn] and empi[pd_dqs]. see empi[pw_dqn] and empi[pd_dqs] register definitions in the pxa3xx processor family vol. ii: memory controller configuration developers manual . table 16: mfp input, output, and i/o pins dc operating conditions symbols description min typical max unit notes input dc operating conditions (vcc = 1.8 v typical) vih input high voltage vcc_high * 0.8 ? vcc_high + 0.3 v 3 v il input low voltage -0.3 ? vcc_high * 0.2 v 3 v hys hysteresis (v it+ - v it- ) 0.4 ? vcc_high * 0.5 v 3 r pullup pullup resistance 40 1 110 200 2 k 4 r pulldown pulldown resistance 40 1 110 200 2 k 5 input dc operating conditions (vcc = 3.0 and 3.3 v typical) vih input high voltage 0.8 * vcc_high ? vcc_high + 0.3 v 3 v il input low voltage -0.3 ? vcc_high * 0.2 v 3 v hys hysteresis (v it+ - v it- ) 0.4 ? vcc_high * 0.5 v 3 r pullup pullup resistance 20 1 45 100 2 k 4 r pulldown pulldown resistance 20 1 45 100 2 k 5 table 15: ddr input, output, and i/o pins ac/dc operating conditions (continued) symbols description min typical max unit notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 137 output dc operating conditions (vcc = 1.8 v typical) v oh 6 1x 2x 3x 4x 6x 8x 10x 12x high-level output voltage absolute load current achieving voh 0.9 * vcc_high ? vcc_high v i oh = (ma min) -0.4 -0.8 -1.2 -1.6 -2.4 -3.2 -4.0 -4.8 v ol 6 1x 2x 3x 4x 6x 8x 10x 12x low-level output voltage absolute load current achieving vol vss ? 0.1 * vcc_high vi ol = (ma min) 0.5 1.0 1.5 2.0 3.0 4.0 5.0 6.0 output dc operating conditions (vccp = 3.0 and 3.3 v typical) v oh 6 1x 2x 3x 4x 6x 8x 10x 12x high-level output voltage absolute load current achieving voh vcc_high * 0.9 ? vcc_high v i oh = (ma min) -1.5 -3.0 -4.5 -6.0 -9.0 -12.0 -15.0 -18.0 v ol 6 1x 2x 3x 4x 6x 8x 10x 12x low-level output voltage absolute load current achieving vol vss ? 0.1 * vcc_high vi ol = (ma min) 1.25 2.5 3.75 5 7.5 10 12.5 15 output dc operating conditions (vcc = 1.8, 3.0 and 3.3 v typical) i oz three-state output leakage current ??40 na? i ddq quiescent supply current ? ? 1 na ? table 16: mfp input, output, and i/o pi ns dc operating conditions (continued) symbols description min typical max unit notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 138 april 6, 2009 released 6.2 oscillator electrical specifications the pxa3xx processors contains two oscillators: a 32.768 khz oscillator and a 13.000 mhz oscillator. each oscillator requires a specific crystal. 6.2.1 32.768 khz oscillator specifications the 32.768 khz crystal is connected between the txtal_in (amplifier input) and txtal_out (amplified output). table 17 lists example 32.768 khz crystal specifications. to drive the 32.768 khz crystal pins from an external source: 1. drive the txtal_in pin with a digital signal that has low and high levels as listed in ta b l e 1 7 . 2. ground the txtal_out pin. table 18 lists example 32.768 khz oscillator specifications. note: 1. max voltage, minimum temperature 2. min voltage, maximum temperature 3. vcc_high references to vcc_io1, vcc_io3, vcc_io4, vcc_io6, vcc_df, vcc_ci, vcc_card1, vcc_card2, vcc_lcd, vcc_usb supplies. 4. use mfprxx[pull_sel] and mfprxx[pullup_en] bits to enable or disable pullups. 5. use mfprxx[pull_sel] and mfprxx[pulldown_en] bits to enable or disable pulldowns. 6. multi-function pin (mfp) drive strength is programmable using mfprxx[drive] bitfield. mfpr register definitions are found in the pxa3xx processor family vol. i: system and timer configuration developers manual. table 16: mfp input, output, and i/o pi ns dc operating conditions (continued) symbols description min typical max unit notes table 17: typical 32.768 khz crystal requirements 1 parameter minimum typical maximum units frequency range ? 32.768 ? khz frequency tolerance ?30 ? +30 ppm frequency stability, parabolic coefficient ? ? ?0.04 ppm/( c ) 2 drive level ? ? 1.0 uw load capacitance (c l ) ? 12.5 ? pf series resistance (r s ) ? 18 85 k ? note: 1. a capacitor is required from txtal_in to ground and from txtal_out to ground. the capacitors must be 22.0 pf, 5%, +/-30ppm/c temperature coefficient. table 18: typical external 32.768 khz oscillator requirements symbol description min typical max units amplifier specifications www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 139 6.2.2 13.000 mhz oscillator specifications the 13.000 mhz crystal is connected between the pxtal_in (amplifier input) and pxtal_out (amplified output). table 19 lists the 13.000 mhz crystal specifications. to drive the 13.000 mhz crystal pins from an external source: 1. drive the pxtal_in pin with a digital signal with low and high levels as listed in ta bl e 2 0 . 2. float the pxtal_out pin table 20 lists the 13.000 mhz oscillator specifications. vih_x input high voltage, txtal_in 0.8 ? 1.0 v vil_x input low voltage, txtal_in ?0.10 0.00 0.10 v iin_xt input leakage, txtal_in ? ? 10 a cin_xt input capacitance, txtal_in/txtal_out ? 18 25 pf ts_xt stabilization time ? ? 2 s sr_xt slew rate 46 ? ? mv/ s board specifications rp_xt parasitic resistance, txtal_in/txtal_out to any node 20 ? ? m cp_xt parasitic capacitance, txtal_in/txtal_out, total ??5 pf cop_xt parasitic shunt capacitance, txtal_in to txtal_out ??0.4 pf table 18: typical external 32.768 khz oscillator requirements (continued) symbol description min typical max units table 19: typical 13.000 mhz crystal requirements parameter minimum typical maximum units frequency range 12.997 13.000 13.002 mhz frequency tolerance at 25 c ?50 ? +50 ppm oscillation mode fundamental ? maximum change over temperature range ?50 ? +50 ppm drive level ? 10 100 uw load capacitance (c l )?10?pf series resistance (r s )?50? note: no external capacitors are needed on the pxtal_in or pxtal_out pins for use with a 13.000 mhz crystal. the device provides an effective internal load capacitance of 10.0pf which is the load capacitance defined for the frequency tolerance specification. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 140 april 6, 2009 released a 6.2.3 clock outputs 6.2.3.1 clk_pout - 13 mhz clock output clk_pout can be used to drive a buffered version of the pxtal_in oscillator input. refer to table 21 for clk_pout specifications. 6.2.3.2 clk_tout - 32.768 khz clock output a buffered and inverted version of the txtal_in oscillator output is driven out on clk_tout. refer to tab le 2 2 for clk_tout specifications. table 20: typical external 13.000 mhz oscillator requirements symbol description min typical max units amplifier specifications vih_x input high voltage, pxtal_in 1.7 1.8 1.9 v vil_x input low voltage, pxtal_in ?0.10 0.00 0.10 v iin_xp input leakage, pxtal_in ? ? 10 a cin_xp input capacitance, pxtal_in/pxtal_out ? 20 25 pf ts_xp stabilization time ? ? 7 ms sr_xp slew rate 1 ? ? v/ns board specifications rp_xp parasitic resistance, pxtal_in/pxtal_out to any node 20 ? ? m cp_xp parasitic capacitance, pxtal_in/pxtal_out, total ? ? 5 pf cop_xp parasitic shunt capacitance, pxtal_in to pxtal_out ? ? 0.4 pf note clk_pout is available only when software sets the oscc[pen] bit. table 21: clk_pout specifications parameter specifications frequency 13 mhz frequency accuracy (derived from 13 mhz crystal) +/-200 ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20ps max load capacitance (c l )50 pf max rise and fall time (tr & tf) 15 ns max with 50 pf load www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 141 do not route clk_tout close to the 32 khz crystal or the 32 khz crystal signals txtal_in and txtal_out. incorrect layout can cause the 32 khz crystal to not lock, or to lock at an incorrect frequency. note clk_tout is enabled by default. clk_tout can be disabled by writing to the oscc[tensx] bits. table 22: clk_tout specifications parameter specifications frequency 32.768 khz frequency accuracy (derived from 32 khz crystal) +/-200 ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20 ps max load capacitance (c l ) 50 pf max rise and fall time (tr & tf) 15 ns max with 50 pf load www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 142 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 143 7 ac characteristics this chapter includes ac characteristics, timing diagrams and timing parameters for the pxa3xx processor family controllers/interfaces listed below. all memory devices connect to either the external-memory pin interface (empi) or the data-flash interface (dfi). ? empi: ddr sdram timing diagrams and specifications ? dfi: variable latency i/o (vlio) timing diagrams and specifications ? dfi: flash memory timing diagrams and specifications ? dfi: sram timing diagrams and specifications ? dfi: compact flash timing diagrams and specifications ? dfi: nand timing diagrams and specifications ? quick capture camera interface timing diagrams and specifications ? lcd timing diagrams and specifications ? ssp timing diagrams and specifications ? ac ?97 timing diagrams and specifications ? usb 2.0 timing diagrams and specifications (pxa32x and pxa30x only) ? multimedia card timing diagrams and specifications ? secure digital (sd/sdio) timing diagrams and specifications ? jtag boundary scan timing diagrams and specifications a pin?s alternating-current (ac) characteristics include input and output capacitance. these factors determine the loading for external drivers and other load analyses. the ac characteristics also include a derating factor, which indicates how much the ac timings might vary with different loads. table 23 shows the ac operating conditions for the high- and low-strength input, output, and i/o pins. all ac specification values are valid for the device?s entire temperature range. 7.1 external memory pin interface (empi) memory timings this section describes the timing diagrams and timing parameters for the dynamic memory controller (dmemc) on the external memory pin interface (empi). the following diagrams are included in this section: ? figure 52, ddr sdram timing diagrams ? figure 53, md<31:0> to dqs write skew ? figure 54, clk to address/command write skew table 23: standard input, output, and i/o-pin ac operating conditions symbol description min typical max units c in input capacitance, all standard input and i/o pins ? ? 10 pf c out_h output capacitance, all standard high-strength output and i/o pins 20 ? 50 pf c out_l output capacitance, all standard low-strength output and i/o pins 20 ? 50 pf www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 144 april 6, 2009, released ? figure 55, dqs to clk write skew ? figure 56, md<31:0> to dqs read skew 7.1.1 ddr sdram timing diagrams and specifications figure 52 shows the ddr sdram timings that are programmable through the mdcnfg[dtc[1:0]] register. refer the lp ddr jedec spec for complete timing diagrams and specifications. figure 53 shows the dq to dqs skew during write cycles. figure 54 shows the clk to address/command skew during write cycles. figure 52: ddr sdram timing diagrams nop act nop read nop pre nop act nop write nop pre nop 1111 mask0 mask1 mask6 mask7 tcl twr trcd trp trc trcd trp tras trcd trc tras trcd sdclk[1] sdcke command nsdcs[0] nsdras nsdcas nwe dqs md<31:0> dqm[1:0] figure 53: md<31:0> to dqs write skew tdqtva tdqtvb tdqtvb dqs md<31:0> figure 54: clk to address/command write skew tatva tatvb tatvb clock add/cmd www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 145 figure 55 shows the dqs to clk skew during write cycles. figure 56 shows the dq to dqs allowable skew during read cycles. figure 55: dqs to clk write skew tdqstvb tdqstva clock dqs figure 56: md<31:0> to dqs read skew table 24: ddr timing specifications symbol description min typical max units notes t rc nsdras cycle time 5 mdcnfg[dtcx] 10 sdclk 1 t rp nsdras precharge 2 mdcnfg[dtcx] 4 sdclk 1 t cl nsdras to first data valid delay 2 mdcnfg[dtcx] 3 sdclk 1 t ras nsdras active time (min) 3 mdcnfg[dtcx] 6 sdclk 1 t rcd nsdras assert to nsdcas assert delay 2 mdcnfg[dtcx] 4 sdclk 1 t wr write recovery time 2 sdclk 2 t dqtvb dq valid time before dqs 1.38 ? ? ns t dqtva dq valid time after dqs 1.16 ? ? ns t atvb cmd/ctl valid time before clk 3.2 ? ? ns t atva cmd/ctl valid time after clk 3.0 ? ? ns t dqstvb dqs falling edge before clk 3.14 ? ? ns t dqstva dqs falling edge after clk 2.98 ? ? ns t dqdqs skew between dq and dqs permitted at the input. -1.2 ? 1.2 ns note: 1. sdclk frequency is one half of the ddr controller frequency. the ddr controller frequency is configured using accr[dmcfs] bits. 2. the write recovery time is hardcoded to two sdclks. 3. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the mdcnfg register. tdqdqs tdqdqs dqs md<31:0> www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 146 april 6, 2009, released 7.2 data-flash interface (dfi) memory timing specifications this section describes the timing diagrams and timing parameters for all supported memory devices on the data-flash interface (dfi). the following diagrams are included in this section: ? figure 57, vlio read timing diagram ? figure 58, vlio read timing diagram (latched addressing mode) ? figure 59, vlio low order addressing read timing diagram ? figure 60, vlio low order addressing read timing diagram (latched addressing mode) ? figure 61, vlio write timing diagram ? figure 62, vlio write timing diagram (latched addressing mode) ? figure 63, vlio low order addressing write timing diagram ? figure 64, vlio low order addressing write timing diagram (latched addressing mode) ? figure 65, flash asynchronous read timing diagram ? figure 66, flash asynchronous read timing diagram (latched addressing mode) ? figure 67, flash asynchronous low-order read timing diagram ? figure 68, flash asynchronous low-order read timing diagram (latched addressing mode) ? figure 69, flash synchronous read timing diagram ? figure 70, flash synchronous read timing diagram (latched addressing mode) ? figure 71, flash asynchronous write timing diagrams ? figure 72, flash asynchronous write timing diagrams (latched addressing mode) ? figure 73, flash asynchronous low-order addressing write timing diagrams ? figure 74, flash asynchronous low-order addressing write cycle timing diagram ? figure 75, synchronous write timings diagrams ? figure 76, synchronous write timings diagrams (latched addressing mode) ? figure 77, sram asynchronous read timing diagram. ? figure 78, sram asynchronous read timing diagram (latched addressing mode) ? figure 79, sram asynchronous low-order addressing read timing diagram ? figure 80, sram asynchronous read timing diagram (non-aa/d addressing mode) ? figure 81, sram asynchronous write timing diagram ? figure 82, sram asynchronous write timing diagram (latched addressing mode) ? figure 83, sram asynchronous low-order addressing write timing diagram ? figure 84, sram asynchronous low-order addressing write timing diagram (latched addressing mode) ? figure 85, compact flash 16-bit common memory read timing diagram ? figure 86, compact flash 16-bit common memory write timing diagram. ? figure 87, compact flash 16-bit i/o memory read timing diagram ? figure 88, compact flash 8-bit i/o space write timing diagram. ? figure 89, nand flash program timing diagram ? figure 90, nand flash erase timing diagram ? figure 91, nand flash small block read timing diagram ? figure 92, nand flash large block read timing diagram ? figure 93, nand flash status read timing diagram ? figure 94, nand flash id read timing diagram ? figure 95, nand flash reset timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 147 7.2.1 variable latency i/o (vlio) timing diagrams and specifications the variable-latency i/o (vlio) interface allows the use of a data-ready input signal, rdy, to insert a variable number of memory-cycle wait states. the data-bus width for vlio on the dfi for each chip-select region supports 16-bit memory devices. df_noe is asserted for all reads; df_nwe is asserted for all writes. in addition, vlio read accesses differ from sram read accesses in that the df_noe toggles for each beat of a burst. the memory controller waits indefinitely for the rdy signal to be asserted. this wait period hangs the system if the external vlio is not responding. to prevent indefinite system hangs, set the watchdog timer when starting a vlio transfer, and reset the system if no response is received from the vlio. for reads, nbe<1:0> are asserted to 0b00. during writes, data pins are actively driven by the processor (that is, they are not three-stated), regardless of the state of the individual nbe pins. for these writes, the nbe pins are used as byte enables. 7.2.1.1 vlio read timing figure 57 illustrates a full latch-addressing mode read cycle for a vlio device. figure 58 illustrates a full latch-addressing mode read cycle for a vlio device using the latched-addressing mode (pxa31x and pxa30x only). refer to table 25 for detailed timing parameters. only one byte enable (nbe[1:0]) is asserted on a single byte read. figure 57: vlio read timing diagram 1 u add l add rd0 ladd+2 rd1 "00" trds toel trdh taoh tocs toel taos trdh taoh taos taadvh tadvl taadvs tadvl taadvh tadvl tadvl taadvs taadvh tadvl tadvl taadvs tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren nbe[1:0] rdnwr www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 148 april 6, 2009, released 7.2.1.2 vlio low-order addressing read timing figure 59 illustrates a low-order addressing mode read cycle for a vlio device. figure 60 illustrates a low-order addressing mode read cycle for a vlio device using the latched- addressing mode (pxa31x and pxa30x only). refer to table 25 for detailed timing parameters. only one byte enable (nbe[1:0]) is asserted on a single byte read. figure 58: vlio read timing diagram (latched addressing mode) 1 u add l add rd0 ladd+2 rd1 "00" trds toel trdh taoh tocs toel taos trdh taoh taos taadvh tadvl taadvs tadvl taadvh tadvl tadvl taadvs taadvh tadvl tadvl taadvs tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren nbe[1:0] rdnwr figure 59: vlio low order addressing read timing diagram 1 u add l add rd0 rd1 "00" trds trds tocs trdh taoh toel (2 waits) taos toel (2 waits) taoh trdh taos tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 149 7.2.1.3 vlio write timing figure 61 illustrates a full latch-addressing mode write cycle for a vlio device. figure 62 illustrates a full latch-addressing mode write cycle for a vlio device using the latched-addressing mode (pxa31x and pxa30x only). refer to ta b l e 2 5 for detailed timing parameters. figure 60: vlio low order addressing read timing diagram (latched addressing mode) 1 u add l add rd0 rd1 "00" trds trds tocs trdh taoh toel (2 waits) taos toel (2 waits) taoh trdh taos tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] figure 61: vlio write timing diagram 1 u add l add wd0 ladd+2 wd1 "00" m0 "00" m1 txews twel (2 waits) twcs tdwh twel (2 waits) tdws tdwh twel (0 waits) tdws twel (0 waits) tadvl taadvh taadvs tadvl taadvh tadvl taadvs tadvl tadvl taadvh tadvl taadvs ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 150 april 6, 2009, released 7.2.1.4 vlio low order addressing write timing figure 63 illustrates a low-order addressing mode write cycle for a vlio device. figure 64 illustrates a low-order addressing mode write cycle for a vlio using the latched-addressing mode (pxa31x and pxa30x only). refer to ta b l e 2 5 for detailed timing parameters. figure 62: vlio write timing diagram (latched addressing mode) 1 u add l add wd0 ladd+2 wd1 "00" m0 "00" m1 txews twel (2 waits) twcs tdwh twel (2 waits) tdws tdwh twel (0 waits) tdws twel (0 waits) tadvl taadvh taadvs tadvl taadvh tadvl taadvs tadvl tadvl taadvh tadvl taadvs ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] figure 63: vlio low order addressing write timing diagram 1 u add l add wd0 wd1 "00" m0 m1 txews twel (2 waits) twcs tdwh tawh taws tdws twel (2 waits) twel (0 waits) tawh tdwh twel (0 waits) tdws taadvh tadvl tadvl taadvs taadvh tadvl tadvl taadvs ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 151 figure 64: vlio low order addressing write timing diagram (latched addressing mode) table 25: vlio timing specifications symbol description min 2 min 3 min 4 typical max units notes t aadvs address setup to nlla/nlua asserted 011csa drcfgx[alt] 1 df_sclk 1 t aadvh address hold from nlla/nlua deasserted 011csa drcfgx[alt] 1 df_sclk 1 t tadvl nlla/nlua assert time 112csa drcfgx[alw] 7 df_sclk 1 t xews nxcvren setup to df_nwe asserted 111 mcs0/1[rdn] 15 df_sclk 1 t dws byte enables and write data setup to df_nwe asserted ??? 1 ? df_sclk 1 t dwh write data, byte enables and nxcvren hold from df_nwe de-asserted 111 mcs0/1[rdn] 15 df_sclk 1 t aoh address hold from df_noe de-asserted 111 mcs0/1[rdn] 15 df_sclk 1 t wcs df_nwe de-asserted to ncs de-asserted 111 mcs0/1[rdn] 15 df_sclk 1 t ocs df_noe de-asserted to ncs de-asserted 111 mcs0/1[rdn] 15 df_sclk 1 1 u add l add wd0 wd1 "00" m0 m1 txews twel (2 waits) twcs tdwh tawh taws tdws twel (2 waits) twel (0 waits) tawh tdwh twel (0 waits) tdws taadvh tadvl tadvl taadvs taadvh tadvl tadvl taadvs ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe rdy nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 152 april 6, 2009, released 7.2.2 flash memory timing diagrams and specifications the dfi bus uses the static memory controller (smemc) to interface to 16-bit aa/d muxed flash memory. figure 65 through figure 76 show the timing diagrams for asynchronous reads, synchronous reads, asynchronous writes, and synchronous writes. an asynchronous flash read timing is shown in figure 65 . for reads, nbe<1:0> are asserted to 0b00. during flash writes, nbe<1:0> are asserted to 0b00. flash accesses are always 16-bit, so they are not used. 7.2.2.1 flash asynchronous read timing figure 65 illustrates a full latch-addressing mode asynchronous read cycle for a flash device. figure 66 illustrates a full latch-addressing mode asynchronous read cycle for a flash device using the latched addressing mode (pxa31x and pxa30x only). refer to table 26 for detailed timing parameters. t wel df_nwe assert time 3 4 7 mcs0/1[rdf]+ 1 + waits 5 16 df_sclk 1 t oel df_noe assert time 3 4 7 mcs0/1[rdf]+ 1 + waits 5 16 df_sclk 1 t aws address setup to df_nwe assert 111 mcs0/1[rdn] 15 df_sclk 1 t awh address hold from df_nwe de-assert 111 mcs0/1[rdn] 15 df_sclk 1 t aos address setup to df_noe assert 111 mcs0/1[rdn] 15 df_sclk 1 t aoh address hold from df_noe de-assert 111 mcs0/1[rdn] 15 df_sclk 1 t rdh read data hold from sample???0 ? ns 1 t rds read data setup time 30 30 30 ? ? ns 1 tmbtominimum bus turnover time???1 ?df_sclk 1 note: 1. df_sclk frequency depends on the accr[smcfs] and memclkcfg[df_clkdiv] programmed value. 2. df_sclk = 52mhz 3. df_sclk = 104mhz 4. df_sclk = 208mhz 5. waits are cycles inserted while the rdy signal is low. 6. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the csadrcfgx and mcs0/1 registers. table 25: vlio timing specifications (continued) symbol description min 2 min 3 min 4 typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 153 7.2.2.2 flash asynchronous low-order read timing figure 67 illustrates a low-order addressing mode asynchronous read cycle for a flash device. figure 68 illustrates a low-order addressing mode asynchronous read cycle for a flash device using the latched-addressing mode (pxa31x and pxa30x only). refer to table 26 for detailed timing parameters. figure 65: flash asynchronous read timing diagram figure 66: flash asynchronous read timing diagram (latched addressing mode) 0 1 u add l add rd0 ladd+2 rd1 "00" toel toel trdh toel trdl toel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] d f_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rd_nwr nbe[1:0] 1 u add l add rd0 ladd+2 rd1 "00" toel toel trdh toel trdl toel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rd_nwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 154 april 6, 2009, released 7.2.2.3 flash synchronous read timing figure 69 illustrates continuous-word burst mode flash-read cycles. figure 70 illustrates continuous-word burst mode flash-read cycles using the latched-addressing mode (pxa31x and pxa30x only). refer to ta bl e 2 6 for detailed timing parameters. figure 67: flash asynchronous low-order read timing diagram figure 68: flash asynchronous low-order read timing diagram (latched addressing mode) 0 1 u add l add rd0 rd1 "00" tocs trdl trdl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto trdh tmbto trdh tmbto tmbto taoh taoh ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] 0 1 u add l add rd0 rd1 "00" tocs trdl trdl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto trdh tmbto trdh tmbto tmbto taoh taoh ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 155 7.2.2.4 flash asynchronous write timing figure 71 illustrates full latch-mode asynchronous flash-write cycles. figure 72 illustrates full latch-mode asynchronous flash-write cycles using the latched-addressing mode (pxa31x and pxa30x only). refer to ta bl e 2 6 for detailed timing parameters. figure 69: flash synchronous read timing diagram figure 70: flash synchronous read timing diagram (latched addressing mode) laddr[3:0] u add l add d0 d1 d2 d14 d15 "00" tsdh tsda tocs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_sclk ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] laddr[3:0] u add l add d0 d1 d2 d14 d15 "00" tsdh tsda tocs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_sclk addr[25:16] addr[15:4] ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 156 april 6, 2009, released 7.2.2.5 flash asynch ronous low-order addressing write timing figure 73 illustrates a low-order addressing mode asynchronous flash-write cycle. figure 74 illustrates a low-order addressing mode asynchronous flash-write cycle using the latched- addressing mode (pxa31x and pxa30x only). refer to table 26 for detailed timing parameters. figure 71: flash asynchronous write timing diagrams figure 72: flash asynchronous write timing diagrams (latched addressing mode) 0 1 u add l add wd0 ladd+2 wd1 "00" twel tdwh twcs twel tdws twel tdwh twel tdws tadvl taadvh taadvs tadvl taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] 1 u add l add wd0 ladd+2 wd1 "00" twel tdwh twcs twel tdws twel tdwh twel tdws tadvl taadvh taadvs tadvl taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 157 7.2.2.6 synchronous write timings figure 75 illustrates synchronous flash-write cycles. figure 76 illustrates synchronous flash-write cycles using the latched-addressing mode (pxa31x and pxa30x only). refer to table 26 for detailed timing parameters. figure 73: flash asynchronous low-order addressing write timing diagrams 0 1 u add l add wd0 wd1 "00" twel tdwh twcs taws tdws twel twel tawh tdwh tdws twel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] figure 74: flash asynchronous low-order addressing write cycle timing diagram 1 u add l add wd0 wd1 "00" twel tdwh twcs taws tdws twel twel tawh tdwh tdws twel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 158 april 6, 2009, released figure 75: synchronous write timings diagrams figure 76: synchronous write timings diagrams (latched addressing mode) table 26: dfi flash timing specifications symbol description min typical max units notes t aadvh address hold from nlla/nlua de-asserted 0 csadrcfgx[alt] 1df_sclk 1 t aadvs address setup to nlla/nlua asserted 0 csadrcfgx[alt] 1df_sclk 1 t advl nllu/nlla assert time 1 csadrcfgx[alw] 7df_sclk 1 0 1 2 14 15 u add l add wd0 wd1 wd2 wd14 wd15 "00" m0 m1 m2 m14 m15 tsdh tsda twcs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_sclk ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] 1 2 14 15 u add l add wd0 wd1 wd2 wd14 wd15 "00" m0 m1 m2 m14 m15 tsdh tsda twcs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_sclk addr[25:16] addr[15:4] ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 159 7.2.3 sram timing diagrams and specifications an sram read timing is shown in figure 77 . for reads, nbe<1:0> are asserted to 0b00. during writes, data pins are actively driven by the processor (that is, they are not three-stated), regardless of the state of the individual nbe pins. the nbe pins are used as byte enables for these writes. the sram accesses shown in figure 77 and figure 84 illustrate the low-order address mode that uses the df_addr<3:0> bus to change the address without having to go through the time-consuming address-latching process that uses the nlua and nlla signals. t dws data, byte enables, and xcvren setup to df_nwe asserted ? 1 ? df_sclk 1 t dwh data, byte enables, and xcvren hold from df_nwe de-asserted ? 1 ? df_sclk 1 t wcs df_nwe de-asserted to ncs de-asserted ? 1 ? df_sclk 1 t ocs df_noe de-asserted to ncs de-asserted ? 6 ? df_sclk 1 t wel df_nwe assert time 1 mcs0/1[rdf] +1 16 df_sclk 1 t oel df_noe assert time 2 mcs0/1[rdf] + 2 17 df_sclk 1 t rdl df_noe assertion to read data latch 1 mcs0/1[rdf] + 1 16 df_sclk 1 t aos address setup to df_noe assert ? 1 ? df_sclk 1 t awh address hold from df_nwe de-assert ? 1 ? df_sclk 1 t aws address setup to df_nwe assert ? 1 ? df_sclk 1 t aoh address hold from data sample ?1 ? df_sclk 1 t rdh read data hold from sample (asynchronous reads) ? 1 ? df_sclk 1 t sdh synchronous flash read data hold time 4 sxcnfg[sxcl2] + 1 11 df_sclk 1 t sda synchronous flash read data access time 3 sxcnfg[sxcl2] 10 df_sclk 1 t sdh synchronous write data hold time 4 sxcnfg[sxwrcl2] + 1 11 df_sclk 1 t sda synchronous write data access time 3 sxcnfg[sxwrcl2] 10 df_sclk 1 t mbto minimum bus turnover time ? 1 ? df_sclk 1 note: 1. df_sclk frequency depends on the accr[smcfs] and memclkcfg[df_clkdiv] programmed values. 2. the maximum df_sclk frequency for synchronous accesses is 52 mhz. 3. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the csadrcfgx, sxcnfg and mcs0/1 registers. table 26: dfi flash timing specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 160 april 6, 2009, released 7.2.3.1 sram asynchronous read timing figure 77 illustrates a full latch-addressing mode asynchronous-sram read cycle. figure 78 illustrates a full latch-addressing mode asynchronous-sram read cycle using the latched- addressing mode (pxa31x and pxa30x only). refer to table 27 for detailed timing parameters. 7.2.3.2 sram asynchronous low- order addressing read timing figure 79 illustrates a low-order addressing mode asynchronous-sram read cycle. figure 79 illustrates a low-order addressing mode asynchronous-sram read cycle using the latched- addressing mode (pxa31x and pxa30x only). refer to table 27 for detailed timing parameters. figure 77: sram asynchronous read timing diagram. 0 1 u add l add rd0 ladd+2 rd1 "00" toel toel trdh toel trdl toel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rd_nwr nbe[1:0] figure 78: sram asynchronous read timing diagram (latched addressing mode) 1 u add l add rd0 ladd+2 rd1 "00" toel toel trdh toel trdl toel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto tmbto tmbto tmbto tmbto tmbto tmbto tmbto ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rd_nwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 161 7.2.3.3 sram asynchronous write timing figure 81 illustrates a full latch-addressing mode asynchronous-sram write cycle. figure 82 illustrates a full latch-addressing mode asynchronous-sram write cycle using the latched- addressing mode (pxa31x and pxa30x only). refer to ta bl e 2 7 for detailed timing parameters. figure 79: sram asynchronous low-order addressing read timing diagram 0 1 u add l add rd0 rd1 "00" tocs trdl trdl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto trdh tmbto trdh tmbto tmbto taoh taoh ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] figure 80: sram asynchronous read timing diagram (non-aa/d addressing mode) 0 1 u add l add rd0 rd1 "00" tocs trdl trdl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tmbto trdh tmbto trdh tmbto tmbto taoh taoh ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 162 april 6, 2009, released 7.2.3.4 sram asynchronous low- order addressing write timing figure 83 illustrates a low-order addressing mode asynchronous-sram write cycle. figure 84 illustrates a low-order addressing mode asynchronous-sram write cycle using the latched addressing mode (pxa31x and pxa30x only). refer to ta bl e 2 7 for detailed timing parameters. figure 81: sram asynchronous write timing diagram figure 82: sram asynchronous write timing diagram (latched addressing mode) 1 u add l add wd0 ladd+2 wd1 "00" m0 00 m1 twel tdwh twcs twel tdws twel tdwh twel tdws tadvl taadvh taadvs tadvl taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] 1 u add l add wd0 ladd+2 wd1 "00" twel tdwh twcs twel tdws twel tdwh twel tdws tadvl taadvh taadvs tadvl taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 163 figure 83: sram asynchronous low-order addressing write timing diagram 0 1 u add l add wd0 wd1 "00" m0 m1 twel tdwh twcs taws tdws twel twel tawh tdwh tdws twel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] d f_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] figure 84: sram asynchronous low-order addressing write timing diagram (latched addressing mode) 1 u add l add wd0 wd1 "00" m0 m1 twel tdwh twcs taws tdws twel twel tawh tdwh tdws twel taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl ncs[x] addr[25:16] addr[15:4] df_addr[3:0] df_io[15:0] nlua nlla df_noe df_nwe nxcvren rdnwr nbe[1:0] www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 164 april 6, 2009, released table 27: dfi sram timing specifications symbol description min 2 min 3 min 4 typical max units notes t aadvs address setup to nlla/nlua asserted 1 1 1 csadrcfgx[alt] 1 df_sclk 1 t aadvh address hold from nlla/nlua deasserted 1 1 1 csadrcfgx[alt] 1 df_sclk 1 t advl nlla/nlua assert time 1 1 2 csadrcfgx[alw] 7 df_sclk 1 t dws data, byte enables, and xcvren setup to df_nwe asserted ? ? ? 1 ? df_sclk 1 t dwh data, byte enables, and xcvren hold from df_nwe deasserted ? ? ? 1 ? df_sclk 1 t wcs df_nwe de-asserted to ncs de-asserted ? ? ? 1 ? df_sclk 1 t ocs df_noe de-asserted to ncs de-asserted ? ? ? 1 ? df_sclk 1 t wel df_nwe assert time 2 2 3 mcs0/1[rdn] + 1 16 df_sclk 1 t oel df_noe assert time 3 4 7 mcs0/1[rdf] + 2 17 df_sclk 1 t rdl df_noe assertion to read data latch 2 3 6 mcs0/1[rdf] + 1 16 df_sclk 1 t aws address setup to df_nwe assert ??? 1 ? df_sclk 1 t awh address hold from df_nwe de-assert ??? 1 ? df_sclk 1 t aoh address hold from data sample ??? 1 ? df_sclk 1 t rdh read data hold from sample ??? 1 ? df_sclk 1 t mbto minimum bus turnover time ??? 1 ? df_sclk 1 note: 1. df_sclk frequency depends on the accr[smcfs] and memclkcfg[df_clkdiv] programmed values. 2. df_sclk = 52 mhz 3. df_sclk = 104 mhz 4. df_sclk = 208 mhz 5. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the csadrcfgx and mcs0/1 registers. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 165 7.2.4 compact flash timing diagrams and specifications the pxa32x processor card interface provides control for one card, supports 8- and 16-bit peripherals, and handles common memory, i/o, and attribute-memory accesses. the duration of each access is based on programmed values per address space by fields within the mcmemx, mcattx, and mciox registers. the processors are described in detail in the pxa3xx processor family vol. ii: memory controller configuration developers manual . 7.2.4.1 compact flash 16-bit common memory read timing. table 85 illustrates a read cycle from compact flash common memory. refer to tab l e 2 8 for detailed timing parameters. figure 85: compact flash 16-bit common memory read timing diagram uadd ladd uadd rd[15:0] uadd tcmd x_asst_hold x_hold tcmd x_asst_wait x_set tadvl taadvh taadvs tadvl taadvh tadvl taadvs tadvl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_io[15:0] nlua nlla npce1 npce2 niois16 df_nwe df_noe npwait nxcvren rdnwr www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 166 april 6, 2009, released 7.2.4.2 compact flash 16-bit common memory write timing. table 86 illustrates a write cycle to compact flash common memory. refer to tab l e 2 8 for detailed timing parameters. 7.2.4.3 compact flash 16-bit i/o space read timing table 87 illustrates a 16-bit read cycle from compact flash i/o space memory. refer to ta b l e 2 8 for detailed timing parameters. 7.2.4.4 compact flash 8-bit i/o space write timing. table 88 illustrates a 8-bit write cycle to compact flash i/o space memory. refer to table 28 for detailed timing parameters. figure 86: compact flash 16-bit common memory write timing diagram. uadd ladd uadd wd[15:0] uadd tcxh txcs tcmd x_asst_hold x_hold tcmd x_asst_wait tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_io[15:0] nlua nlla npce1 npce2 niois16 df_nwe df_noe npwait nxcvren rdnwr figure 87: compact flash 16-bit i/o memory read timing diagram uadd ladd uadd rd[15:0] uadd tcmd x_asst_hold x_hold tcmd x_asst_wait x_set tadvl taadvh taadvs tadvl tadvl taadvh tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh taadvs tadvl df_io[15:0] nlua nlla npce1 npce2 niois16 npiow npior npwait nxcvren rdnwr www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 167 figure 88: compact flash 8-bit i/o space write timing diagram. table 28: compact flash timing specifications symbol description min typical max units notes t aadvs address setup to nlla/nlua asserted 0 csadrcfgx[alt] 1 df_sclk 1 t aadvh address hold from nlla/nlua de-asserted 0 csadrcfgx[alt] 1 df_sclk 1 t advl nlla/nlua assert time 1 csadrcfgx[alw] 7 df_sclk 1 t x_hold command de-assert to npce de-assert via nlua command 1 mcx0[hold] 63 df_sclk 1 t x_set address valid to command assert 1 mcx0[set] 127 df_sclk 1 t x_asst_ wait command assert to when npwait is sampled 1 mcx0[0_asst]+1 32 df_sclk 1 t x_asst_h old npwait sample high to command de-asserted 1 (2*mcx0[0_asst])+1 63 df_sclk 1 t xcs nxcvren assert to command assert 1 mcx0[set] 127 df_sclk 1 t cxh command de-assert to nxcvren de-assert 1 mcx0[hold] 63 df_sclk 1 t cmd command assertion time 3 (3*mcx0[0_asst])+3+ waits 96 df_sclk 1 uadd ladd uadd "xx" & wd[7:0] uadd ladd+1 uadd "xx" & wd[15:7] uadd tcxh tcxh txcs txcs tcmd x_asst_hold tcmd x_asst_wait x_set tcmd x_asst_hold x_hold tcmd x_asst_wait x_set taadvh tadvl tadvl taadvs tadvl taadvh taadvs tadvl tadvl taadvh tadvl taadvs taadvh tadvl taadvs tadvl taadvh tadvl tadvl taadvs tadvl taadvs tadvl tadvl taadvh taadvs tadvl df_io[15:0] nlua nlla npce1 npce2 niois16 npiow npior npwait nxcvren rdnwr www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 168 april 6, 2009, released 7.2.5 nand timing diagrams and specifications this section describes the timing diagrams for nand flash programming, erase, read, status read, and id read with timing parameters. 7.2.5.1 nand flash program timing data-flash program operation writes data to the flash. figure 89 illustrates the programming sequence for a flash device with a page size of 512 bytes, and a spare area of 16 bytes. the flash device is addressed in four cycles. refer to tab l e 2 9 for the detailed descriptions of the timing parameters. if the auto-read status bit (auto_rs) is set in the command, the nand flash controller performs a status check (command 0x70) to determine whether the program operation was successful. 7.2.5.2 nand flash erase timing figure 90 illustrates the erase sequence for a flash device. the block to be erased in the flash device is addressed in two cycles. refer to table 29 for the detailed descriptions of the timing parameters. if the auto-read status bit (auto_rs) is set in the command, the data flash controller performs a status check (command 0x70) to determine whether the erase operation was successful. note: 1. df_sclk frequency depends on the accr[smcfs] and memclkcfg[df_clkdiv] programmed values. 6. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the csadrcfgx, mcmemx, mcattx, and mciox registers. table 28: compact flash timing specifications (continued) symbol description min typical max units notes figure 89: nand flash program timing diagram ta(io) ta(io) th(wh) tsu(wl) tsu(wl) tsu(wl) tsu(wl) th(wh) th(wh) th(wh) twrcycle twrcycle tw(wh) tw(wh) tw(wl) tw(wl) 80h addr1 addr2 addr3 addr4 din0 din1 din527 10h 70h status nd_ncsx nd_cle nd_nwe nd_ale nd_nre nd_iox nand_rnb www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 169 7.2.5.3 small block nand flash read timing figure 91 illustrates the read sequence for a small-block flash device. the flash device is addressed in four cycles. refer to tab l e 2 9 for detailed descriptions of the timing parameters. 7.2.5.4 large block nand flash read timing figure 92 illustrates the read sequence for a large-block flash device. the flash device is addressed in four cycles. refer to tab l e 2 9 for detailed descriptions of the timing parameters. figure 90: nand flash erase timing diagram tw(rl) tsu(wl) td(ahwl) tsu(wl) th(wh) th(wh) th(wh) th(io) tsu(io) th(io) tsu(io) tw(wl) tw(wh) tw(wl) tw(wh) 0x60 70h status addr2 addr1 0xd0 nd_ncsx nd_cle nd_nwe nd_ale nd_nre nd_iox nand_rnb figure 91: nand flash small block read timing diagram tw(rh) tw(rl) td(whrl) th(wh) tw(wh) tw(wl) tsu(wl) tsu(wl) th(wh) th(wh ) th(io) tsu(io) trdcycle trdcycle trdcylce trdcylce 00h addr1 addr2 addr3 addr4 dout0 dout1 dout511 nd_ncsx nd_cle nd_nwe nd_ale nd_nre nd_iox n and_rnb www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 170 april 6, 2009, released 7.2.5.5 nand flash status read timing figure 93 illustrates the status-read sequence for a flash device. refer to table 29 for detailed descriptions of the timing parameters. 7.2.5.6 nand flash id read timing figure 94 illustrates the id read sequence for a flash device. refer to table 29 for detailed descriptions of the timing parameters. figure 92: nand flash large block read timing diagram 30h tw(rh) tw(rl) td(whrl) th(wh) tsu(wl) tw(wh) tw(wl) tsu(wl) tsu(wl) th(wh) th(wh) th(io) tsu(io) trdcycle trdcycle 00h addr1 addr2 addr3 addr4 dout0 dout1 dout2112 nd_ncsx nd_cle nd_nwe nd_ale nd_nre nd_iox nand_rnb figure 93: nand flash status read timing diagram tw(rl) td(whsrl) tw(wl) tsu(wl) th(wh) th(io) tsu(io) tw(wh) tw(wh) 70h status nd_ncsx nd_cle nd_nwe nd_nre nd_iox www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 171 7.2.5.7 nand flash reset timing figure 95 illustrates the reset sequence for a flash device. refer to table 29 for detailed descriptions of the timing parameters. 7.2.5.8 nand flash timing parameters table 29 provides the values for the timing parameters seen in figure 89 , figure 90 , figure 91 , figure 92 , figure 92 , figure 93 , figure 94 and figure 95 . figure 94: nand flash id read timing diagram th(wh) tsu(wl) th(wh) th(wh) th(io) tsu(io) tw(rh) tw(rl) tw(rh) tw(rl) td(alrl) tsu(wl) tw(wl) tw(wl) 0x90 byte 1 byte 2 0x00 nd_ncsx nd_cle nd_nwe nd_ale nd_nre n d_io[7:0] figure 95: nand flash reset timing diagram 0xff tsu(wl) th(wh) nd_cle nd_ncsx nd_nwe nd_ale nd_nre nd_iox nand_rnb table 29: nand flash interface program timing specifications symbol description min 1 min 2 typical max units notes t su(wl) setup time for nd_ale, nd_cle and nd_csx with respect to nd_nwe assertion 1 1 ndtr0cs0[tcs] + 1 8 nclk 3 , 4 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 172 april 6, 2009, released t h(wh) hold time for nd_ale, nd_cle and nd_csx with respect to nd_nwe de-assertion. 2 1 ndtr0cs0[tch] + 1 8 nclk 3 , 4 t w(wl) nd_nwe pulse width during assertion delay 2 1 ndtr0cs0[twp] + 1 8 nclk 3 , 4 t w(wh) nd_nwe pulse width during de-assertion delay 2 1 ndtr0cs0[twh] + 1 8 nclk 3 , 4 t w(rl) nd_nre pulse width during assertion delay 4 1 ndtr0cs0[trp] + 1 16 nclk 3 , 4 t w(rh) nd_nre pulse width during de-assertion delay 3 1 ndtr0cs0[trh] + 1 8 nclk 3 , 4 t d(whrl) nd_nwe high to nd_nre low delay for read 3 3 (ndtr1cs0[tr] + 2) + (ndtr0cs0[tch] + 1) 65536 nclk 3 , 4 t d(whsrl) nd_nwe high to nd_nre low delay for status read 1 1 ndtr1cs0[twhr] 5 , 6 32 nclk 3 , 4 t d(alrl) nd_ale high to nd_nre low delay for id read 1 1 ndtr1cs0[tar] 7 , 8 16 nclk 3 , 4 t a(io) nd_iox data access time 2.5 2.5 ? 10 ns ? t su(io) nd_iox setup time constraint 23 23 ? ? ns ? t h(io) nd_iox hold time constraint 23 23 ? ? ns ? t rdcycle read cycle times 67.31 30 ? ? ns ? t wrcycle write cycle times 38.46 30 ? ? ns ? note: 1. pxa32x processor only 2. pxa31x processor and pxa30x processor only 3. nclk represents the clock period using a 156 mhz clock on the pxa31x processor and pxa30x processor. 4. nclk represents the clock period using a 104 mhz clock on the pxa32x processor 5. if ndtr0cs1[tar] + ndtr0cs0[tch] >= ndtr0cs1[twhr] delay = ndtr0cs0[tch] + (ndtr0cs1[tar] + 2) 6. if ndtr0cs1[tar] + ndtr0cs0[tch] < ndtr0cs1[twhr] delay = (ndtr0cs1[twhr] + 1) 7. if ndtr0cs1[tar] + ndtr0cs0[tch] >= ndtr0cs1[twhr] delay = ndtr0cs1[tar] + 1 8. if ndtr0cs1[tar] + ndtr0cs0[tch] < ndtr0cs1[twhr] delay = (ndtr0cs1[twhr] - ndtr0cs0[tch]) 9. refer to the pxa3xx processor family vol. ii: memory controller configuration developers manual for more information on the ndtr0cs0 and ndtr0cs1 registers. table 29: nand flash interface program timing specifications (continued) symbol description min 1 min 2 typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 173 7.3 quick capture camera interface timing diagrams and specifications this section describes the timing diagrams for master-parallel mode of operation with timing parameters. 7.3.1 master-parallel timing the master-parallel interface timing is shown in figure 96 . see ta b l e 3 0 for camera timing parameters. the frame clock (c_fv) must first be asserted to indicate that a new frame has begun. the valid data is then captured with the active edge of pclk, after beginning of line wait count (cicr2[blw]) pclk cycles have elapsed from the assertion of c_lv. at the end of the capture of the last line of a frame, the quick capture interface waits for the assertion of c_fv to begin the next frame-capture sequence. 7.3.2 master-parallel interface timing specifications table 30 describes the camera timing parameters for figure 96 . figure 96: camera master-parallel timing diagram tw(m) tw(pl) tw(pl) tw(ph) tw(ph) tw(ml) tw(ml) tw(mh) tw(mh) th(p) tsu(p) tw(p) tw(p) line0 data line1 data line n data n=lpf-1 c _mclk (optional) c_pclk c_fv c_lv c_ddx table 30: master-parallel timing specifications (pxa32x processor and pxa30x processor only) symbol description min typical max units notes t w(m) c_mclk pulse width frequency 0.48 ? 52 mhz t w(p) c_pclk pulse width frequency 3.0 ? 48 mhz 1 t w(mh) c_mclk pulse width high time 9.5 ? 4352 ns t w(ml) c_mclk pulse width low time 9.5 ? 4352 ns t w(ph) c_pclk pulse width high time 10 ? 158.3 ns t w(pl) c_pclk pulse width low time 10 ? 158.3 ns t su(p) c_ddx to c_pclk setup time constraint 2.2 ? ? ns t h(p) c_pclk to c_ddx hold time constraint 3.0 ? ? ns www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 174 april 6, 2009, released 7.3.3 slave-parallel timing figure 97 shows the timing for slave-parallel mode of operation. see tab le 3 2 for the slave-parallel timing parameters. the timing is very similar to that of master-slave, except that in slave-parallel mode, the quick capture interface drives the synchronization signals c_lv and c_fv. c_fv and c_lv are driven for the duration specified by vertical sync width (cicr3[vsw]) and horizontal sync width (cicr2[hsw]), respectively. the delay (in pclk cycles) between c_fv being asserted and c_lv being asserted is configured with cicr2[bfpw]. the number of frame clock (c_fv) periods to wait before valid data is output is configured with cicr2[fsw]. note: 1. maximum allowable frequency of c_pclk is 1/4 of system bus #1 (application subsystem clock configuration register (accr[hss])). table 30: master-parallel timing specifications (continued)(pxa32x processor and pxa30x symbol description min typical max units notes table 31: master-parallel timing specifications (pxa31x processor only) symbol description min typical max units notes t w(m) c_mclk pulse width frequency 0.48 ? 52 mhz t w(p) c_pclk pulse width frequency 3.0 ? 96 mhz 1 t w(mh) c_mclk pulse width high time 9.5 ? 4352 ns t w(ml) c_mclk pulse width low time 9.5 ? 4352 ns t w(ph) c_pclk pulse width high time 4.95 ? 158.3 ns t w(pl) c_pclk pulse width low time 4.95 ? 158.3 ns t su(p) c_ddx to c_pclk setup time constraint 2.2 ? ? ns t h(p) c_pclk to c_ddx hold time constraint 3.0 ? ? ns note: 1. maximum allowable frequency of c_pclk is 1/2 of system bus #1 (application subsystem clock configuration register (accr[hss])) note before the quick capture interface starts operating in this mode, configure the sensor to float the synchronization pins. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 175 7.3.4 slave-parallel interface timing parameters table 32 describes the camera timing parameters for figure 97 . 7.4 lcd timing diagrams and specifications this section describes the timing diagrams for interfacing to passive, active, and smart lcd panels with timing parameters. 7.4.1 lcd passive timing for passive (and active) lcd panels, the line-clock pin (l_lclk_a0) is toggled when an entire line of pixels has been output to the lcd controller screen. likewise, the frame-clock pin (l_fclk_rd) is toggled when an entire frame of pixels has been output to the lcd controller screen. switch the power and ground supplies periodically to prevent a dc charge from building within a passive display. the lcd controller signals the display to switch the polarity by toggling the ac bias pin (l_bias). program the number of line-clock transitions between each toggle to control the frequency of the bias pin. figure 97: camera slave-parallel timing diagram tw(m) tw(pl) tw(pl) tw(ph) tw(ph) tw(ml) tw(ml) tw(ml) tw(ml) th(p) tsu(p) tw(p) tw(p) line0 data line1 data line n data n=lpf-1 c _mclk (optional) c_pclk c_fv c_lv c_ddx table 32: slave-parallel timing specifications symbol description min typical max units notes t w(m) c_mclk pulse width frequency 0.203 ? 52 mhz t w(p) c_pclk pulse width frequency 3.0 ? 6.25 mhz t w(mh) c_mclk pulse width high time 9.5 ? 2338 ns t w(ml) c_mclk pulse width low time 9.5 ? 2338 ns t w(ph) c_pclk pulse width high time 76 ? 158.3 ns t w(pl) c_pclk pulse width low time 76 ? 158.3 ns t su(p) c_ddx to c_pclk setup time constraint 3.7 ? ? ns t h(p) c_pclk to c_ddx hold time constraint 0.0 ? ? ns www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 176 april 6, 2009, released the programmable timing of the line- and frame-clock pins supports both passive and active mode. programming options include: wait-state insertion both at the beginning and end of each line and frame; pixel clock; line clock; frame clock; output-enable signal polarity; and frame-clock pulse width. figure 98 and figure 99 illustrate the lcd timing parameters. tab le 3 3 provides the values for the parameters. figure 98: lcd passive panel synchronous timing diagram row 0 row 1 row 2 row n row 0 row 1 tw(p) td(lddv) blw=0 tw(vsp) vsw=0 tw(hsp) hsw=1 tw(l) td(dvla) elw =0 tw(f) l_fclk_rd l_lclk_a0 l _pclk_wr ldd<17:0> figure 99: lcd passive panel data timing diagram data th(dvp) tsu(pdv) lclk l_pclk_wr > copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 177 7.4.2 lcd active panel timing for active (and passive) lcd panels, the line clock pin (l_lclk_a0) is toggled when an entire line of pixels has been output to the lcd controller screen. likewise, the frame-clock pin (l_fclk_rd) is toggled when an entire frame of pixels has been output to the lcd controller screen. the pixel clock toggles continuously in this mode as long as the lcd is enabled. the ac bias pin (l_bias) functions as an output enable. when l_bias is asserted, the display latches data from the lcd pins using the pixel clock. the line-clock pin (l_lclk_a0) is used as the horizontal synchronization signal, and the frame clock (l_fclk_rd) as the vertical synchronization signal. the programmable timing of the line- and frame-clock pins supports both passive and active mode. programming options include: wait-state insertion both at the beginning and end of each line and frame; pixel clock; line clock; frame clock; output-enable signal polarity; and frame-clock pulse width. t w(hsp) horizontal sync pulse width 1 lccr1[hsw] + 1 64 tw(p) 1 , 4 t w(vsp) vertical sync pulse width 1 lccr2[vsw] + 1 64 tw(l) 1 t d(lddv) beginning-of-line l_pclk_wr wait delay 1 lccr1[blw] + 1 256 tw(p) 1 , 5 t d(dvla) end-of-line l_pclk_wr wait delay 1 lccr1[elw] + 1 256 tw(p) 1 t su(pdv) l_pclk_wr to data valid set up time when pclk divisor is an even number ??2 9 + 0.5ns lclk 5 , 6 , 7 t su(pdv) l_pclk_wr to data valid set up time when pclk divisor is an odd number ?? (divisor - 1))/2) 9 + 0.5ns lclk 5 , 6 , 7 t h(dvp) end-of-line l_pclk_wr hold time when pclk divisor is an even number. 2 9 + 0.5ns ? ? lclk 5 , 6 , 7 t h(dvp) end-of-line l_pclk_wr hold time when pclk divisor is an odd number (((divisor - 1)/2) + 1) 9 + 0.5ns ?? lclk 5 , 6 , 7 note: 1. pclk is short for pixel clock. 2. pixel clock is programmable based off lclk. lclk frequency depends on the accr[hss] programmed value. 3. in this example, horizontal-sync polarity as shown is active high, inactive low. use lccr3[hsp] for configuring polarity. 4. in this example vertical-sync polarity is active high, inactive low. use lccr3[vsp] for configuring polarity. 5. in this example pixel-clock polarity is configured to sample data on the rising edge of l_pclk_wr (lccr3[pcp]=0). 6. in this example the lclk is 104 mhz and the divisor is 5 (20.8 mhz). 7. the divisor is determined by the lccr3[pcd] register. the setup and hold times are different depending on the divisor value. 8. lclk can vary from104 mhz to 208 mhz. refer to the pxa3xx processor family vol. iii: graphics and input controller configuration developers manual , for more information. 9. lclk clock cycles 10. there are no beginning-of-frame lclk wait to end-of-frame lclk wait delay timings for passive panels. lccr2[bfw] and lccr2[efw] must be zero for passive panels. table 33: lcd passive panel timing specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 178 april 6, 2009, released figure 100 and figure 101 illustrate the lcd timing parameters. ta b l e 3 4 provides the values for the parameters. figure 100:lcd active panel timing diagram figure 101:lcd active panel timing diagram line 0 line 1 line 2 line n td(lddv) blw=0 tw(p) tw(l) td(dvla) elw=1 td(fdld) bfw=1 tw(hsp) hsw=1 tw(f) td(lafa) tw(vsp) vsw=0 l_fclk_rd l_lclk_a0 l_ bias l _pclk_wr ldd<17:0> data th(dvp) tsu(pdv) lclk l_pclk_wr > copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 179 7.4.3 lcd smart panel timing figure 102 illustrates the lcd timing parameters for smart panels. ta bl e 3 5 provides the values for the parameters. t d(lddv) beginning-of-line l_pclk_wr wait delay 1 lccr1[blw] + 1 256 tw(p) 1 , 5 t d(dvla) end-of-line l_pclk_wr wait delay 1 lccr1[elw] + 1 256 tw(p) 1 t d(fdld) beginning-of-frame lclk wait delay 0 lccr2[bfw] 255 pclk 1 t d(lafa) end-of-frame lclk wait delay 0 lccr2[efw] 255 ns ? t su(pdv) l_pclk_wr to data valid set up time when pclk divisor is an even number ?? 2 11 + 0.5ns lclk 5 , 6 , 7 t su(pdv) l_pclk_wr to data valid set up time when pclk divisor is an odd number ?? (divisor - 1))/2) 11 + 0.5ns lclk 8 , 9 , 10 t h(dvp) end-of-line l_pclk_wr hold time when pclk divisor is an even number. 2 11 + 0.5ns ??lclk 8 , 9 , 10 t h(dvp) end-of-line l_pclk_wr hold time when pclk divisor is an odd number (((divis or - 1)/2) + 1) 11 + 0.5ns ??lclk 8 , 9 , 10 note: 1. pclk is shortened form of pixel clock. 2. pixel clock is programmable based off lclk. lclk frequency depends on the accr[hss] programmed value. 3. in this example, horizontal-sync polarity as shown is active high, inactive low. use lccr3[hsp] for configuring polarity. 4. in this example vertical-sync polarity is active high, inactive low. use lccr3[vsp] for configuring polarity. 5. in this example pixel-clock polarity is configured to sample data on the rising edge of l_pclk_wr (lccr3[pcp]=0). 6. in this example the lclk is 104 mhz and the divisor is 5 (20.8 mhz). 7. the divisor is determined by the lccr3[pcd] register. the setup and hold times are different depending on the divisor value. 8. in this example pixel-clock polarity is configured to sample data on the rising edge of l_pclk_wr (lccr3[pcp]=0). 9. in this example the lclk is 104 mhz and the divisor is 5 (20.8 mhz). 10. the divisor is determined by the lccr3[pcd] register. the setup and hold times are different depending on the divisor value. 11. lclk clock cycles 12. lclk can vary from104 mhz to 208 mhz. refer to the pxa3xx processor family vol. iii: graphics and input controller configuration developers manual , for more information. table 34: lcd active panel timing specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 180 april 6, 2009, released figure 102:lcd smart panel timing diagram dwr_hld rd_pulwd a0csrd_set wr_pulwd dwr_set a0cswr_set a0csrd_hl cmd_inh a0cswr_hld l_cs l_lclk_a0 l _pclk_wr l_fclk_rd l_lddx table 35: lcd smart panel timing specifications symbol description min typical max units notes t a0cswr_set l_cs low to l_pclk_wr low delay 1 lccr1[elw] + 1 256 lclk 1 t wr_pulwd l_pclk_wr pulse width duration 1 lccr1[blw] + 1 256 lclk 1 t dwr_set lddx write data setup before pclk_wr low 1 lccr1[elw] + 1 256 lclk 1 t a0cswr_hld l_pclk_wr high to l_cs high delay 1 lccr1[elw] + 1 256 lclk 1 t dwr_hld l_lddx write data hold after l_pclk_wr high 1 lccr1[elw] + 1 256 lclk 1 t cmd_inh l_cs recover time for two consecutive read or writes (include write/read and read/write) 1 lccr3[pcd] + 1 256 lclk 1 t a0csrd_set l_cs low to l_fclk_rd low delay 1 lccr1[elw] + 1 256 lclk 1 t rd_pulwd l_fclk_rd pulse width duration 1 lccr1[blw] + 1 256 lclk 1 t a0csrd_hld l_fclk_rd high to l_cs high delay 1 lccr1[elw] + 1 256 lclk 1 note: 1. lclk frequency depends on the accr[hss] programmed value. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 181 7.5 ssp timing diagrams and specifications figure 103 and tab l e 3 6 convey the ssp timing parameters with ssp in master mode. the processor drives sspsclk and sspsfrm when in master mode. figure 104 and tab l e 3 7 convey the ssp timing parameters with ssp in slave mode. the processor receives sspsclk and sspsfrm when in slave mode. the processor can also provide sspsclk while the external peripheral sources sspsfrm, which is termed a ?mixed mode? as in shown in figure 105 with the timing parameters specified in table 38 . similarly, the processor can also receive sspsclk while the external peripheral provides sspsfrm, which is termed a ?mixed mode? as in shown in figure 106 with the timing parameters specified in tab l e 3 9 . ssp master mode timing figure 103:ssp master mode timing diagram th(t) tsu(t) tw(ch) tw(cl) th(r) tsu(r) sspsclk s spsfrm ssptxd ssprxd table 36: ssp master mode timing specifications symbol description min max units notes t w(ch) sspsclk pulse width high duration 38.46 ? ns 1 t w(ch) sspsclk pulse width high duration 19.23 ? ns 2 t w(cl) sspsclk pulse width low duration 38.46 ? ns 1 t w(cl) sspsclk pulse width low duration 19.23 ? ns 2 t su(t) ssptxd to sspsclk setup time 35 ? ns t h(t) sspsclk to ssptxd hold time 33 ? ns t su(r) ssprxd to sspsclk setup time 4 ? ns t h(r) sspsclk to ssprxd hold time 3.6 ? ns note: 1. timing for pxa32x and pxa30x only 2. timing for pxa31x only www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 182 april 6, 2009, released 7.5.1 ssp slave mode timing figure 104:ssp slave mode timing definitions th(t) tsu(t) th(r) tsu(r) tw(ch) tw(cl) tw(ch) tw(cl) sspsclk s spsfrm ssptxd ssprxd table 37: ssp slave mode timing specifications symbol description min max units t w(ch) sspsclk pulse width high duration 38.46 ? ns t w(cl) sspsclk pulse width low duration 38.46 ? ns t su(t) ssptxd to sspsclk setup time 35 ? ns t h(t) sspsclk to ssptxd hold time 33 ? ns t su(r) sspsrxd to sspsclk setup time 4 ? ns t h(r) sspsrxd to sspssclk hold time 3.6 ? ns www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 183 7.5.2 ssp mixed mode timing - processor master to clock figure 105:ssp mixed mode, processor master to clock timing definitions th(t) tsu(t) tw(ch) tw(cl) th(r) tsu(r) sspsclk s spsfrm ssptxd ssprxd table 38: ssp mixed mode, processor master to clock timing specifications symbol description min max units notes t w(ch) sspsclk pulse width high duration 38.46 ? ns 1 t w(ch) sspsclk pulse width high duration 19.23 ? ns 2 t w(cl) sspsclk pulse width low duration 38.46 ? ns 1 t w(cl) sspsclk pulse width low duration 19.23 ? ns 2 t su(t) ssptxd to sspsclk setup time 35 ? ns t h(t) sspsclk to ssptxd hold time 33 ? ns t su(r) sspsrxd to sspsclk setup time 4 ? ns t h(r) sspsrxd to sspssclk hold time 3.6 ? ns note: 1. timing for pxa32x and pxa30x only 2. timing for pxa31x only www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 184 april 6, 2009, released 7.5.3 ssp mixed mode timing - processor master to frame 7.6 ac ?97 timing diagrams and specifications figure 107 and tab l e 4 0 defines the ac ?97 codec interface ac timing specifications. figure 106:ssp mixed mode, processor master to frame timing definitions table 39: ssp mixed mode, processor master to frame timing specifications symbol description min max units notes t w(ch) sspsclk pulse width high duration 38.46 ? ns 1 t w(ch) sspsclk pulse width high duration 19.23 ? ns 2 t w(cl) sspsclk pulse width low duration 38.46 ? ns 1 t w(cl) sspsclk pulse width low duration 19.23 ? ns 2 t su(t) ssptxd to sspsclk setup time 35 ? ns t h(t) sspsclk to ssptxd hold time 33 ? ns t su(r) sspsrxd to sspsclk setup time 4 ? ns t h(r) sspsrxd to sspssclk hold time 3.6 ? ns note: 1. 0timing for pxa32x and pxa30x only 2. 0timing for pxa31x only th(t) tsu(t) th(r) tsu(r) tw(ch) tw(cl) tw(ch) tw(cl) sspsclk s spsfrm ssptxd ssprxd www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 185 7.7 usb 2.0 timing diagrams and specifications (pxa32x and pxa30x only) figure 108 and tab l e 4 1 defines the ac characteristics for the usb 2.0 timing specifications. figure 107:ac ?97 codec timing diagram tw(s) td(bh-sdv) td(bh-sv) th(d) tsu(d) tw(b) tw(b) ac97_reset_n ac97_bitclk ac97_sync ac97_sdata_out ac97_sdata_inx ac97_sysclk table 40: ac ?97 codec timing specifications symbol parameter min max units notes t w(b) ac97_bitclk pulse width constraint 40.69 ? ns 1 t d(bh-sv) ac97_bitclk high to ac97_sync valid delay 8.18 22.68 ns 1 t d(bh-sdv) ac97_bitclk high to ac97_sdata_out valid delay 7.78 23.08 ns 1 t su(d) ac97_sdata_inx to ac97_bitclk setup time constraint 4.33 ? ns 1 t h(d) ac97_bitclk to ac97_sdata_inx hold time constraint 0.93 ? ns 1 t w(s) ac97_sysclk pulse width delay 20.34 ? ns note: 1. slew rate for incoming bitclk is 0.5 v/ns figure 108:usb 2.0 timing diagram valid tdco tcco tdh_min tdsu_min tch_min tcsu_min utm_clk control in data in control out data out www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 186 april 6, 2009, released 7.8 multimedia card timing diagrams and specifications figure 109 and tab l e 4 2 define the multimedia card controller ac timing specifications. table 41: usb 2.0 timing specifications symbol parameter min max unit notes t csu_min minimum setup time for txvalid 4.8 15.5 ns ? t ch_min minimum hold time for txvalid 1 ?ns ? t dsu_min minimum setup time for data in (transmit) 4.8 15.5 ns ? t dh_min minimum hold time for transmit data 1 ?ns ? t cco clock to control out time for txready, rxvalid, rxactive and rxerror 18 ns ? t cdo clock to data out time (receive) 1 8 ns ? figure 109:multimedia card timing diagrams data in invalid data in data out invalid data out toh tosu tih tisu twl tfreq twh twl twh tfreq mmclk mmdat0/1 mmdat2/3 table 42: multimedia card timing specifications symbol parameter min max unit notes t freq mmclk frequency data transfer mode 0 19.5 mhz 2 t freq mmclk frequency data transfer mode 026mhz 3 t freq mmclk frequency identification mode 0 400 khz t wh clock high time 10 ? ns 1 t wl clock low time 10 ? ns 1 t rise clock rise time ? 10 ns 1 t fall clock fall time ? 10 ns 1 t isu data input setup time 3 ? ns 1 t ih data input hold time 3 ? ns 1 t osu output data setup time 13.1 ? ns 1 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 187 7.9 secure digital (sd/sdio) timing diagrams and specifications figure 110 and table 43 define the secure digital (sd/sdio) controller ac timing specifications. t oh output data hold time 9.7 ? ns 1 note: 1. rise and fall times measured from 10% - 90% of voltage level. 2. timing for pxa32x processor only. 3. timing for pxa31x processor and pxa30x processor only. 4. 0 khz is when the clock is stopped. the minimum 100 khz frequency range is where a continous clock is required. table 42: multimedia card timing specifications (continued) symbol parameter min max unit notes figure 110:sd/sdio timing diagrams data in invalid invalid data out td(q) td(id) tih tisu tfreq twh twl twh tfreq twl mmclk mmdat0/1 mmdat2/3 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 188 april 6, 2009, released 7.10 jtag boundary scan timing diagrams and specifications figure 111 and tab l e 4 4 defines the ac specifications for the jtag boundary-scan test signals. table 43: sd/sdio timing specifications symbol parameter min max unit notes t freq mmclk frequency data transfer mode 0 19.5 mhz 2 t freq mmclk frequency data transfer mode 026 mhz 3 t freq mmclk frequency identification mode 0 1 /100 400 khz t wh clock high time 50 ?ns? t wl clock low time 50 ? ns ? t rise clock rise time ? 10 ns 4 t fall clock fall time ? 10 ns 4 t isu data input setup time 5 ?ns? t ih data input hold time 5 ?ns? t d(q) output delay time during data transfer mode 014 ns ? t d(id) output delay time during identification mode 050 ns ? note: 1. 0 khz is when the clock is stopped. the minimum 100 khz frequency range is where continuous clock is required. 2. timing for pxa32x processor only. 3. timing for pxa31x processor and pxa30x processor only. 4. rise and fall times measured from 10% - 90% of voltage level. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009, released page 189 figure 111:jtag boundary-scan timing diagram table 44: boundary scan timing specifications symbol parameter min max units notes tbsf tck frequency 0.0 13 mhz ? tbsch tck high time 15.0 ? ns 3 tbscl tck low time 15.0 ? ns 3 tbscr tck rise time ? 5.0 ns 1 tbscf tck fall time ? 5.0 ns 2 c a p t u r e - i r shift-ir run-test/idle tof1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsih1 tbsis1 tbsih1 tbsis1 tbsih 2 tbsis2 tbscl tbsch tbsf tck ntrst tms tdi tdo c ontroller state t e s t - l o g i c - r e s e t r u n - t e s t / i d l e s e le c t - d r - s c a n s e l e c t - i r - s c a n e x i t 1 - i r u p d a t e - i r t e s t - l o g i c - r e s e t tntrs t www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 190 april 6, 2009, released tbsis1 input setup to tck tdi, tms 4.0 ? ns ? tbsih1 input hold from tck tdi, tms 6.0 ? ns ? tbsis2 input setup to tck ntrst 25.0 ? ns ? tbsih2 input hold from tck ntrst 3.0 ? ns ? tntrst assertion time of ntrst 6 ? ms ? tbsov1 tdo valid delay 1.5 6.9 ns 4 tof1 tdo float delay 1.1 5.4 ns 4 note: 1. not shown in diagram. this is the transition time for tck from 0.8 v to 2.0 v. 2. not shown in diagram. this is the transition time for tck from 2.0 v to 0.8 v. 3. measured at 1.5 v 4. relative to falling edge of tck table 44: boundary scan timing specifications (continued) symbol parameter min max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 191 8 power and reset specifications this section includes specifications for the following: ? power up ? power down ? reset timing ? power consumption 8.1 power up timings the external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operation. figure 112 shows this sequence and is detailed in ta b l e 4 5 . . figure 112:power up reset timing tshroh tsehph tsehph tsehph trsthseh tphlvth tvmhvsh tsehvmh tvmainbfh tbfhrsth tvbhrsth vcc_main vcc_bbatt nreset nbatt_fault sys_en vcc_mvt vcc_sysen pwr_en pwr_scl pwr_sda nreset_out v cc_apps, vcc_sram www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 192 april 6, 2009 released 8.2 powerdown timings this section has the following powerdown timings: ? s2/d3/c4 - sleep ? s3/d4/c4 - deep sleep 8.2.1 s2/d3/c4 mode timings during s2/d3/c4 (sleep) mode, the nreset_out and pwr_en signals change state. the sequence indicated in figure 113 and detailed in tab l e 4 6 is the required timing parameters for s2/d3/c4 mode. table 45: power up timing specifications symbol description min max units notes t vbhrsth vcc_bbatt enabled to nreset high constraint 8 + pmic ramp rate ?ms 1 t vmainbfh vcc_main enabled to nbatt_fault high constraint 0?ms 2 t bfhrsth nbatt_fault high to nreset high constraint 165 ? s 3 t rsthseh nreset high to sys_en high delay ? 2.005 s ? t sehvmh sys_en high to vcc_mvt stable 0 sys_del time s 5 t vmhvsh vcc_mvt enabled to vcc_sysen stable 0 sys_del time - t sehvmh s 4 , 5 t sehph sys_en high to pwr_en high delay 182 sys_del time + 183 s 5 t shroh sys_en high to nreset_out high delay sys_del time + 213 sys_del time + 214 s 5 t phlvth pwr_en high to vcc_apps and vcc_sram supplies stable 0pwr_del time s 6 note: 1. pmic ramp rate is the time for pmic voltages to ramp to the preferred voltage levels. increasing the ramp rate decreases the overall power-up timing. 2. vcc_main is the main battery supply voltage 3. nbatt_fault is the signal that is used to determine if the main power supply is connected. if nbatt_fault occurs after nreset, the processor enters an s3/d4/c4 before going into s0/d0/c0. 4. vcc_sysen = all supplies except vcc_bbatt, vcc_apps, vcc_sram and vcc_mvt. 5. defined by programming pcfr[sys_del] 6. defined by programming pcfr[pwr_del] www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 193 figure 113:s2/d3/c4 timing note: 1. nreset _out assertion is an option for s2/d3/c4 en try. by clearing the pcfr[sl_rod], nreset_out is asserted upon entry into s2/d3/c4. sleep (entry) sleep sleep (exit) normal tphroh tphroh texit tentry twakedetect tphlvth tpllvtl tewhewv tewlewh tewhewv tewlewh wakeup event detected ext_wakeupx pwr_en pwr_scl pwr_sda vcc_apps, vcc_sram nreset_out table 46: s2/d3/c4 timing specifications symbol description min typical max units notes t entry pwrmode s2/d3/c4 state command issued to pwr_en low delay 78 s 4 t pllvtl pwr_en low to vcc_apps and vcc_sram supplies disabled constraint 0? ? s ? t plrol / t phroh pwr_en low to nreset_out low and pwr_en high to nreset_out high delay -62.5 ? 62.5 s 2 t ewlewh ext_wakeupx low pulse width constraint 5? ? ns 1 , 3 t ewhewv ext_wakeupx high pulse width constraint 5? ? ns 1 , 3 t phlvth pwr_en high to vcc_apps and vcc_sram supplies stable ? ? pwr_de l time s 2 t wakedetec t acknowledge the external wake-up edge and to begin the wake-up sequence delay ?? 150 s? t exit wake-up event to the run mode delay ? 7.9 ? ms 4 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 194 april 6, 2009 released 8.2.2 s3/d4/c4 mode timings during s3/d4/c4 (deep sleep) mode, nreset_out, pwr_en and sys_en change state. the sequence indicated in figure 114 and detailed in tab l e 4 7 is the required timing parameters for s3/d4/c4 (deep sleep) mode. note: 1. ext_wakeupx signal shown in the diagram is for falling edge detect. however, either edge or both edge detect can be enabled. pwer[werx] and fwer[wefx] configures which edge is used for detection. 2. s2/d3/c4 state nreset_out disable (pcfr[sl_rod]) ? prevents the nreset_out pin from asserting upon entry into s2/d3/c4 or s3/d4/c4 modes. 3. ext_wakeupx signal shown in this diagram is based of pwer[edf] bit being set. 4. time with pcfr[pwr_del] = 0b0 and no power i 2 c commands. table 46: s2/d3/c4 timing specifications (continued) symbol description min typical max units notes figure 114:s3/d4/c4 timing note: 1. vcc_sysen = all supplies except vcc_bbatt, vcc_apps, vcc_sram and vcc_mvt. 2. nreset _out assertion is an option for s3/d4/c4 entry. by clearing the pcfr[sl_rod], nreset_out is asserted upon entry into s3/d4/c4. deep sleep (entry) deep sleep deep sleep (exit) normal tshroh tdentry trolsl tplsl tsehph tdexit twakedetect tbfhbfl tbflbfh tbfhbfl tbflbfh tvmhvsh tvslvml tlvtlvsl tslvsl tsehmvth tphlvth tpllvtl tewhewv tewlewh tewhewv tewlewh wakeup signal ext_wakeupx pwr_en pwr_scl pwr_sda v cc_apps, vcc_sram sys_en vcc_mvt vcc_sysen nreset_out nbatt_fault www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 195 table 47: s3/d4/c4 (deep sleep) timing specifications symbol description min typical max units notes t dentry pwrmode s3/d4/c4 state command issued to sys_en low delay ?1.4 ?ms 3 , 7 t pllvtl pwr_en low to vcc_apps and vcc_sram supplies disabled constraint 0? ?s? t plsl pwr_en low to sys_en low delay ? ? 62 s? t rolsl nreset_out low to sys_en low delay ? ? 123 s 4 t bflbfh nbatt_fault low pulse width constraint 100 ? ? s t lvtlvsl vcc_apps and vcc_sram supplies disabled to vcc_sysen disabled constraint 0? ?s 2 t slvsl sys_en low to vcc_sysen supplies disabled constraint 0? ?ns 2 , 3 t vslvml vcc_sysen supplies disabled to vcc_mvt supply disabled constraint 0 ? 100 ns 2 t ewlewh ext_wakeupx low to ext_wakeupx high constraint 5? ?ns 1 t ewhewv ext_wakeupx high to ext_wakeupx valid delay 5? ?ns 1 t wakedetect acknowledge the external wake-up edge and to begin the wake-up sequence delay ? ? 150 s 4 t bfhseh nbatt_fault high to sys_en high delay ? ? 150 s? t phlvth pwr_en high to vcc_apps and vcc_sram supplies stable 0 ? pwr_del time s? t sehmvth sys_en to vcc_mvt supply stable 0 ? sys_del time s? t sehph sys_en high to pwr_en high delay 182 ? sys_del time + 183 s? t dexit wakeup event to run mode delay ? oscc[vcx ost] + sys_del + pwr_del + 1ms ms 6 , 7 www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 196 april 6, 2009 released 8.3 reset timing the processor asserts the nreset_out pin in one of several different reset modes: ? hardware reset timing ? watchdog reset timing ? gpio reset timing (can be configured by software) the following sections provide the timing and specifications for the entry and exit of these modes. 8.3.1 hardware reset timing hardware reset timing sequences assume stable power supplies at the assertion of nreset. they follow the timings indicated in section 8.1, power up timings . refer to figure 112 . 8.3.2 watchdog reset timing watchdog reset is an internally generated reset and therefore has no external-pin dependencies. the nreset_out pin is the only indicator of watchdog reset, and it stays asserted for t grlgrh . nbautt_fault and nreset are assumed to be in their asserted states. 8.3.3 gpio reset timing gpio reset is usually generated externally to a dedicated signal ngpio_reset. a gpio reset can also occur by setting the pmcr[swgr] register. figure 115 shows the timing of gpio reset. t vmhvsh vcc_mvt supply enabled to vcc_sysen supplies stable 0 ? sys_del time - t sehvmh s 2 t shroh sys_en high to nreset_out high delay sys_del time + 213 ? sys_del time + 214 s 4 t bfhbfl nbatt_fault high pulse width constraint 0? ?s note: 1. ext_wakeupx signal shown in the diagram is for falling edge detect. however, edge detection can be enabled for either edge or both edges. pwer[werx] and fwer[wefx] configures which edge(s) is/are used for detection. 2. vcc_sysen = all supplies except vcc_bbatt, vcc_apps, vcc_sram and vcc_mvt. 3. to get the most power savings, marvell recommends turning off vcc_sysen as close to the sys_en assertion as possible 4. s2/d3/c4 state nreset_out disable (pcfr[sl_rod]) ? prevents the nreset_out pin from asserting upon entry into s2/d3/c4 or s3/d4/c4 modes. 5. the time interval between the software write to core pwrmode register (cp14 register 7) to initiate a low-power mode and the wake-detection window activation is 1 s (max). 6. the following are the assumptions for exit times - ? there are no transfers pending within the system that cause exit sequence to stall ? there are no external transfers pending that cause exit sequence to stall ? all counters that are user programmable that can cause exit sequence to stall are set to minimum values: including sys_del, pwr_del, lpm_del and vctost ? exit times provided are typical 7. time with pcfr[pwr_del] = 0b0 and no power i 2 c commands. table 47: s3/d4/c4 (deep sleep) timing specifications (continued) symbol description min typical max units notes www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 197 8.4 power consumption power consumption depends on the following: ? operating voltage ? operating frequency ? peripherals enabled ? external switching activity ? external loading table 49 contains pxa32x processor power-consumption information. table 50 contains pxa31x processor power-consumption information. table 51 contains pxa30x processor power-consumption information. . 4 figure 115:gpio reset timing tgrhroh tgrlrol tgrlgrh tgrlgrh ng pio_reset n reset_out ndf_cs2 table 48: gpio reset timing specifications symbol description min max units notes tgrlgrh ngpio_reset pulse width constraint 100 ? s? tgrlrol ngpio_reset low to nreset_out low delay 153 ? s 1 tgrhroh ngpio_reset high to nreset_out high delay 92 ? s 1 note: 1. gpio reset disable (pcfr[gp_rod ])?enables/disables assertion of nreset_out during gpio reset. table 49: pxa32x processor power-consumption specifications 1 parameter description low power typical (mw) low power maximum (mw) standard typical (mw) standard maximum (mw) test conditions active power (turbo/run/switch/system bus) 806 mhz active power (806/403/403/208) ? ? ? 1950 1 208 mhz active power (?/208/208/104) 485 5 ? 582 4 ? 1 104 mhz active power (?/104/104/104) 300 5 ? 360 4 ? 1 low power modes (s3/d4/c4, s2/d3/c4) www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 198 april 6, 2009 released s3/d4/c4 ? ? ? 0.120 2 s2/d3/c4 ? ? ? 0.800 3 test conditions: 1. vcc_apps = 1.4v; vcc_sram = 1.4v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; 8 dma channels with memory to memory transactions 2. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=0v; vcc_mem=0v; ta = 0c 3. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=3v; vcc_mem=1.8v; ta = 0c 4. vcc_apps = 1.1v; vcc_sram = 1.1v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; 8 dma channels with memory to memory transactions 5. vcc_apps = 1.0v; vcc_sram = 1.0v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; 8 dma channels with memory to memory transactions note: 1. numbers are representative of median plus 1 sigma (85% of the units will be below these numbers) 2. vcc_io is a combination of the vcc_io1, vcc_df, vcc_io3, vcc_i04, vcc_ci, vcc_io6, vcc_lcd, vcc_msl,vcc_usb, vcc_card1, vcc_card2 and vcc_ts voltage domains. 3. only voltage domains listed for each test condition were used to measure power consumption. table 49: pxa32x processor power-consumption specifications 1 (continued) parameter description low power typical (mw) low power maximum (mw) standard typical (mw) standard maximum (mw) test conditions table 50: pxa31x processor power-consumption specifications 1 parameter description typical (mw) maximum (mw) test conditions active power (turbo/run/switch/system bus) 624 mhz active power (624/312/312/208) ? 1525 1 low power modes (s3/d4/c4, s2/d3/c4, s0/d2/c2, s0/d1/c2) s3/d4/c4 ? 0.120 2 s2/d3/c4 ? 0.800 3 s0/d2/c2 ? 0.975 4 www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 199 . s0/d1/c2 ? 0.975 5 test conditions: 1. vcc_apps = 1.375v; vcc_sram = 1.375v; vcc_pll = 1. 8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; 8 dma channels with memory to memory transactions 2. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=0v; vcc_mem=0v;ta = 0c 3. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=3v; vcc_mem=1.8v; ta = 0c 4. vcc_bbatt = 3.0v; vcc_apps = 1.4v; vcc_sram =1.4v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; 5. vcc_bbatt = 3.0v; vcc_apps = 1.4v; vcc_sram =1.4v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0c; note: 1. numbers are representative of median plus 1 sigma (85% of the units will be below these numbers) 2. vcc_io is a combination of the vcc_io1, vcc_df, vcc_io3, vcc_ci, vcc_lcd, vcc_msl,vcc_usb, vcc_card1 and vcc_card2 voltage domains. 3. only voltage domains listed for each test condition were used to measure power consumption. table 50: pxa31x processor power-consumption specifications 1 (continued) parameter description typical (mw) maximum (mw) test conditions table 51: pxa30x processor power-consumption specifications 1 parameter description typical (mw) maximum (mw) test conditions active power (turbo/run/switch/system bus) 624 mhz active power (624/312/312/208) ? 1525 1 low power modes (s3/d4/c4, s2/d3/c4, s0/d2/c2, s0/d1/c2) s3/d4/c4 ? 0.120 2 s2/d3/c4 ? 0.800 3 s0/d2/c2 ? 0.975 4 s0/d1/c2 ? 0.975 5 test conditions: 1. vcc_apps = 1.375v; vcc_sram = 1.375v; vcc_pll = 1.8v; vcc_io = .0v; vcc_mem = 1.8v; ta = 0c; 8 dma channels with memory to memory transactions 2. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=0v; vcc_mem=0v;ta = 0c 3. vcc_bbatt = 3.0v; vcc_apps = 0v; vcc_sram = 0v; vcc_pll=0; vcc_io=3v; vcc_mem=1.8v; ta = 0c 4. vcc_bbatt = 3.0v; vcc_apps = 1.4v; vcc_sram =1.4 v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0 c ; 5. vcc_bbatt = 3.0v; vcc_apps = 1.4v; vcc_sram =1.4 v; vcc_pll = 1.8v; vcc_io = 3.0v; vcc_mem = 1.8v; ta = 0 c note: 1. numbers are representative of median plus 1 sigma (85% of the units will be below these numbers) 2. vcc_io is a combination of the vcc_io1, vcc_df, vcc_io3, vcc_ci, vcc_lcd, vcc_msl,vcc_usb, vcc_card1, vcc_card2 and vcc_ulpi voltage domains. 3. only voltage domains listed for each test condition were used to measure power consumption. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 200 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 201 a pxa30x and pxa31x programmer enabling the pxa30x and pxa31x processors are high-performance, low-power microprocessors now available with additional memory chips. a.1 introduction this chapter describes how to prepare the pxa30x and pxa31x processors for flash memory programming, and how to reduce programming time in a factory environment. the pxa30x and pxa31x processors can be enabled to program flash using one of two different methods. one method focuses on programming the pxa30x and pxa31x processor prior to assembly of the system; the other focuses on waiting until after the processors have been assembled in the system before programming. both methods may be suitable, depending on the design requirements. this chapter explains the trade-offs between different methods, thus helping reduce time in a factory environment and/or reducing cost of development. the direct-access programming method requires minimum software development and takes less time to program the flash memory. direct-access programming requires that all other memory devices along with the pxa30x and pxa31x processors be placed into high-z (by issuing a jtag high-z instruction) while programming the nand flash memory. all the power domains must be brought up to their required voltages to prevent damage to the part. all other memories are placed into high-z by applying power and ensuring the de-assertion of their chip-select signals. the second method for programming flash within the pxa30x and pxa31x processors requires a greater amount of code development through the jtag controller. it is a slower programming method but requires fewer pins. this method does not require any of the memory address, data, or control signals to be pinned out. flash loader code is loaded into the pxa30x and pxa31x processors mini-instruction cache. the code is then executed and uses the pxa30x and pxa31x processors memory controller to program the flash and de-select the other memory devices that might be present within the package. this method is referred to as jtag flash programming . all the power domains on pxa30x and pxa31x processors must be brought up to their required voltages to prevent damage to the part. all input signals not used must be driven to prevent excessive current usage. refer to the pxa30x and pxa31x processor developers manual ?debug interface? chapter for jtag-specific command information. a.2 device configuration the pxa30x and pxa31x processors stacked package uses a processor die combined with flash memory die and/or sdram memory chips all packaged together. currently available pxa30x and pxa31x processors package configurations are as follows: ? 1 gbits of nand flash memory + 512 mbits of low-power ddr (pxa30x processor) ? 2 gbits of nand flash memory + 1 gbits of low-power ddr (pxa31x processor) note device configurations are subject to change before final production qualification. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 202 april 6, 2009 released a.3 procedure to prepare pxa3xx (88ap3xx) processor family for programming flash the following steps describe the procedure to prepare the pxa30x processor or pxa31x processor using either the direct-access programming method or the jtag-flash programming method. to prepare for direct-access programming, the internal memories other than flash are de-selected by de-asserting the dedicated chip-select signals and the pxa30x processor or pxa31x processor must be placed into high-z using high-z jtag command. to prepare for jtag flash programming, bring the pxa30x processor or pxa31x processor out of reset. it is responsible for controlling all the memory signals and receiving the data to program the flash devices through the jtag controller. a.3.1 sequence required for direct-access programming follow these steps to prepare the pxa30x processor or pxa31x processor for direct-access programming. use the power-on timing specifications with respect to applying power to the required domains. 1. if required, drive all memory chip selects (other than nand flash) to their inactive state to guarantee the other memories are not contending with the nand flash signals. 2. drive ext_wakeup0 pin low, nbatt_fault pin high, and ngpio_reset pin high. 3. apply a hardware reset to the package by asserting nreset and ntrst together. 4. release reset by de-asserting nreset and ntrst together. 5. wait for nreset_out to de-assert. 6. issue the high-z jtag command (0x002) to place the pxa30x processor or pxa31x processor signals into high-z state. 7. begin programming the flash devices in the package. figure 116:diagram showing steps for putting pxa30x processor and pxa31x processor into high-z te s t- l o gic- re se t run - test/idle s e le c t-dr- s c a n sele c t-ir-scan cap ture-ir shift-highz instruction e x i t1 - ir u p date-ir ru n- t e s t/id l e tck ntrst tms tdi oll er state www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 203 a.3.2 sequence required for jtag flash programming follow the steps below to prepare the pxa30x processor or pxa31x processor for jtag flash programming. use the power-on timing specifications with respect to applying power to the required domains. 1. drive ext_wakeup0 pin low, nbatt_fault pin high, and ngpio_reset pin high. 2. apply a hardware reset to the package by asserting nreset and ntrst together. 3. release jtag reset by de-asserting ntrst. 4. follow steps documented in download code in the instruction cache seen in the pxa30x and pxa31x processor developers manual. 5. download the flash loader utility into the mini-instruction cache, start execution of the flash loader utility. 6. 10 s must elapse after ntrst is de-asserted before proceeding with any jtag operation. 7. de-assert nreset. 8. wait for nreset_out to de-assert. 9. begin sending raw data through the jtag port to program the flash devices in the package. a.4 pxa30x processor or pxa31x processor: connections for flash programming table 53 describes the connections for existing pxa30x processor or pxa31x processor configurations. tab l e 5 3 shows the minimum number of balls that must be connected to program the nand flash memory internal to the package for each of the two programming methods as described in section a.3 . for direct-access flash programming, the balls needed are determined based on the power signals and control signals required for placing the pxa30x and pxa31x processors into a high-z state. for the jtag-flash programming method, the signals needed are only those that power up the pxa30x and pxa31x processors such that the jtag controller can program flash through the pxa30x and pxa31x processors memory controllers. table 53 shows the connections required for programming the nand flash memory within the pxa30x and pxa31x processors. the first two columns in table 53 show which signals must be accessed depending on the method used to program the nand flash memory. use the list in the next table to decode the letter representing the die within the pxa30x and pxa31x processors. . table 52: abbreviations used in table 53 f ball required to program flash b ball required by the pxa30x and pxa31x processors s ball required to deselect sdram v voltage supply connection required nc no connect rfu reserved for future use dnu do not use. do not physically connect to anything o optional (may not be required depending on system design) shade shading indicates ball is used differently between pxa30x processor and pxa31x processor. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 204 april 6, 2009 released table 53: required balls for programming the package flash memory required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction power control signals (vcc_bbatt) b b d3 pwr_en pwr_en ? use power-on timing specifications. b b d4 sys_en sys_en ? b b d6 nreset_in nreset_in ? b b f9 nreset_out nreset_out ? b b b7 ext_wakeup 0 ext_wakeup 0 ? pull-down to ground. this signals internal pull-down is enabled during power-on, hardware, global watchdog and gpio resets and is disabled when the pcfr[pudh] bit is set. b b c6 nbatt_fault nbatt_fault ? pull-up to vcc_bbatt. b b e8 ngpio_reset ngpio_reset ? pull-up to vcc_bbatt. this signals internal pull-up is enabled during power-on, hardware, global watchdog and gpio resets and is disabled when the pcfr[pudh] bit is set. b b a7 pwr_cap0 pwr_cap0 ? external 0.1 f capacitor connected between pwr_cap0 and pwr_cap1. if a polarized capacitor is used, the + plate must be connected to pwr_cap1. b b f8 pwr_cap1 pwr_cap1 ? b b c7 pwr_out pwr_out ? external 0.1 f capacitor connected to ground. www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 205 jtag interface (vcc_bbatt) b b a6 ntrst ntrst ? jtag interface. b b c4 tck tck ? bb e3 tdi tdi ? b b d2 tdo tdo ? bb c3 tms tms ? processor clock signals b b a8 txtal_in txtal_in ? can be connected to an external 32.768 khz crystal or to an external clock source. note: the maximum voltage level on txtal_in is 1.0 v. b b b8 txtal_out txtal_out ? can be connected to an external 32.768 khz crystal or grounded when an external clock source is connected to txtal_in. processor clock signals b b b9 pxtal_in pxtal_in ? must be connected to a 13 mhz crystal or external clock source. b b c9 pxtal_out pxtal_out ? must be connected to a 13 mhz crystal or left floating when using an external clock source. test signals b b b11 test test ? reserved for manufacturing test. must be grounded for normal operation. b b f11 testclk testclk ? reserved for manufacturing test. must be grounded for normal operation. table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 206 april 6, 2009 released data flash interface (vcc_df) f w3 df_int_rnb df_int_rnb r/b nand read/busy . must have an external 10 kohm pull-up to vcc_df. f aa5 df_io0 df_io0 i/o<0:15 > nand i/o interface. f aa6 df_io1 df_io1 f w7 df_io2 df_io2 f y8 df_io3 df_io3 f v10 df_io4 df_io4 f w13 df_io5 df_io5 f w12 df_io6 df_io6 f v11 df_io7 df_io7 f u8 df_io8 df_io8 f y5 df_io9 df_io9 f y6 df_io10 df_io10 f w8 df_io11 df_io11 f u15 df_io12 df_io12 f w10 df_io13 df_io13 f w11 df_io14 df_io14 f w15 df_io15 df_io15 f v7 df_ale_nwe df_ale_nwe ale ale - address latch enable table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 207 f v9 df_ncs0 df_ncs0 ce ce - chip enable. note: refer to individual package specifications to determine which chip enables to use for programming nand. f u10 df_ncs1 df_ncs1 f w5 df_nre df_nre re re - read enable f w4 df_nwe df_nwe we we - write enable f v8 df_cle_noe df_cle_noe cle cle - command latch enable f u5 df_nwp df_nwp wp wp - write protect. when logic low, provides a hardware protection against undesired modify (program / erase) operations. must be connected to vcc_df when programming nand. no connect signals rfu c1, n2, v2, w2, u3, b4, g4, l4, p4, c5, p5, l8, m8, d19, aa19 rfu rfu ? reserved for future use. treat as a no connect. dnu w9 dnu dnu do not use. do not physically connect to anything. power supplies table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 208 april 6, 2009 released v v l5, n5, aa7, aa9, a10, h10, p10, h11, p11, h12, p12, aa12, a13, y13, k14, l14, m14, a15, n21 vcc_apps vcc_apps ? apply 1.41 v v v aa8, c18, b19 vcc_sram vcc_sram ? v v c8 vcc_bbatt vcc_bbatt ? apply 3.3 v v v d12, aa16 vcc_pll vcc_pll ? apply 1.8 v v v e4, j5, t5, g9, u9, g14, r14, h15, j15, n15 vcc_mvt vcc_mvt ? v v d9 vcc_osc13m vcc_osc13m ? v v d10 vcc_bg vcc_bg ? v v y11 vcc_card1 vcc_card1 ? apply 3.3 v v v aa14 vcc_card2 vcc_card2 ? v v e15, g10, g15 vcc_io1 vcc_io1 ? v v t16 vcc_io3 vcc_io3 ? v v k16, l16, m16 vcc_lcd vcc_lcd ? v v g17 vcc_msl vcc_msl ? table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 209 v v b3 vcc_usb vcc_bias ? apply 3.3 v for both processors v v p15, p20 vcc_ci vcc_ci ? apply 3.3 v v v r16 rfu vcc_ulpi ? apply 1.8 v for pxa31x processor v v d5, g5, v5, g6, h6, j6, k6, l6, m6, n6, p6, r6, t6, u6 vcc_mem vcc_mem ? apply 1.8 v. v v g11, t9, t10, t11, t12, t13 vcc_df vcc_df vcc (for nand) apply 1.8 v. v v c2, f4, k5, m5, r5, y7, h8, r8, t8, a9, h9, p9, b13, h13, p13, aa13, h14, j14, n14, p14, t14, b16, a20, b20, n20, a21, b21 vss vss ? connect to ground. v v d8 vss_bbatt vss_bbatt ? connect to ground. v v c10 vss_bg vss_bg ? connect to ground. v v y12 vss_card1 vss_card1 ? connect to ground. v v aa15 vss_card2 vss_card2 ? connect to ground. v v p19 vss_ci vss_ci ? connect to ground. table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 210 april 6, 2009 released a.5 pxa30x processor and pxa31x processor processor mechanical drawings refer to section 3 for the pxa30x and pxa31x processors mechanical drawings. v v y1, aa1, y2, aa2, r9, r10, r11, g12, r12, r13 vss_df vss_df vss (for nand) connect to ground. v v g13, f15 vss_io1 vss_io1 ? connect to ground. vv t15, y20, aa20, y21, aa21 vss_io3 vss_io3 ? connect to ground. v v k15, l15, m15 vss_lcd vss_lcd ? connect to ground. v v f6, f7, g7, h7, j7, k7, l7, m7, n7, p7, r7, t7, u7 vss_mem vss_mem ? connect to ground. v v f17 vss_msl vss_msl ? connect to ground. v v e9 vss_osc13m vss_osc13m ? connect to ground. v v d7 vss_osc32k vss_osc32k ? connect to ground. v v e11, e12, w16 vss_pll vss_pll ? connect to ground. v v a1, b1, a2, b2 vss_usb vss ? connect to ground. v v r15 rfu vss_ulpi ? connect to ground for pxa31x processor. table 53: required balls for programming the package flash memory (continued) required balls (jtag flash programming) required balls (direct access programming) ball # pxa30x processor function pxa31x processor function nand function signal instruction www.datasheet.co.kr datasheet pdf - http://www..net/
copyright ? 2009 marvell doc. no. mv-s105156-00 rev. 2.0 version - april 6, 2009 released page 211 a.6 pxa30x processor and pxa31x processor processor ballouts refer to section 4 for the pxa30x and pxa31x processors ballouts. www.datasheet.co.kr datasheet pdf - http://www..net/
pxa3xx (88ap3xx) processor family electrical, mechanical, and thermal functional specification doc. no. mv-s105156-00 rev. 2.0 version - copyright ? 2009 marvell page 212 april 6, 2009 released www.datasheet.co.kr datasheet pdf - http://www..net/
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